XC3190A-3PQ160C Xilinx Inc, XC3190A-3PQ160C Datasheet - Page 13
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XC3190A-3PQ160C
Manufacturer Part Number
XC3190A-3PQ160C
Description
IC LOGIC CL ARRAY 9000GAT 160PQF
Manufacturer
Xilinx Inc
Series
XC3000A/Lr
Datasheet
1.XC3190A-3PC84C.pdf
(76 pages)
Specifications of XC3190A-3PQ160C
Number Of Labs/clbs
320
Total Ram Bits
64160
Number Of I /o
138
Number Of Gates
6000
Voltage - Supply
4.25 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
160-BQFP
Dc
9929
Case
QFP160
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Logic Elements/cells
-
Other names
122-1047
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3190A-3PQ160C
Manufacturer:
XILINX
Quantity:
455
Part Number:
XC3190A-3PQ160C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Longlines
The Longlines bypass the switch matrices and are intended
primarily for signals that must travel a long distance, or
must have minimum skew among multiple destinations.
Longlines, shown in
tally the height or width of the interconnect area. Each inter-
connection column has three vertical Longlines, and each
interconnection row has two horizontal Longlines. Two
additional Longlines are located adjacent to the outer sets
of switching matrices. In devices larger than the XC3020A
and XC3120A FPGAs, two vertical Longlines in each col-
November 9, 1998 (Version 3.1)
Figure 14: Horizontal and Vertical Longlines. These Longlines provide high fan-out, low-skew signal distribution in
each row and column. The global buffer in the upper left die corner drives a common line throughout the FPGA.
R
Figure
Product Obsolete or Under Obsolescence
14, run vertically and horizon-
XC3000 Series Field Programmable Gate Arrays
umn are connectable half-length lines. On the XC3020A
and XC3120A FPGAs, only the outer Longlines are con-
nectable half-length lines.
Longlines can be driven by a logic block or IOB output on a
column-by-column basis. This capability provides a com-
mon low skew control or clock line within each column of
logic blocks. Interconnections of these Longlines are
shown in
input to a Longline and are enabled automatically by the
development system when a connection is made.
Figure
15. Isolation buffers are provided at each
7-15
7