XC3190A-3PQ160C Xilinx Inc, XC3190A-3PQ160C Datasheet - Page 18
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XC3190A-3PQ160C
Manufacturer Part Number
XC3190A-3PQ160C
Description
IC LOGIC CL ARRAY 9000GAT 160PQF
Manufacturer
Xilinx Inc
Series
XC3000A/Lr
Datasheet
1.XC3190A-3PC84C.pdf
(76 pages)
Specifications of XC3190A-3PQ160C
Number Of Labs/clbs
320
Total Ram Bits
64160
Number Of I /o
138
Number Of Gates
6000
Voltage - Supply
4.25 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
160-BQFP
Dc
9929
Case
QFP160
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Logic Elements/cells
-
Other names
122-1047
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3190A-3PQ160C
Manufacturer:
XILINX
Quantity:
455
Part Number:
XC3190A-3PQ160C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
XC3000 Series Field Programmable Gate Arrays
A re-program is initiated.when a configured XC3000 series
device senses a High-to-Low transition and subsequent >6
pin is externally held permanently Low, a High-to-Low tran-
sition and subsequent >6 s Low time on the RESET pack-
age pin.
The device returns to the Clear state where the configura-
tion memory is cleared and mode lines re-sampled, as for
an aborted configuration. The complete configuration pro-
gram is cleared and loaded during each configuration pro-
gram cycle.
Length count control allows a system of multiple Field Pro-
grammable Gate Arrays, of assorted sizes, to begin opera-
tion in a synchronized fashion. The configuration program
7-20
Figure 21: Internal Configuration Data Structure for an FPGA. This shows the preamble, length count and data
frames generated by the Development System.
The Length Count produced by the program = [(40-bit preamble + sum of program data + 1 per daisy chain device)
rounded up to multiple of 8] – (2
added if roundup increment is less than K. K additional clocks are needed to complete start-up after length count is
reached.
Gates
CLBs
Row x Col
IOBs
Flip-flops
Horizontal Longlines
TBUFs/Horizontal LL
Bits per Frame
(including1 start and 3 stop bits)
Frames
Program Data =
Bits x Frames + 4 bits
(excludes header)
PROM size (bits) =
Program Data
+ 40-bit Header
s Low level on the DONE/PROG package pin, or, if this
Device
*The LCA Device Require Four Dummy Bits Min; Software Generates Eight Dummy Bits
11111111
0010
< 24-Bit Length Count >
1111
0 <Data Frame # 001 > 111
0 <Data Frame # 002 > 111
0 <Data Frame # 003 > 111
0 <Data Frame # 196 > 111
0 <Data Frame # 197 > 111
1111
.
.
.
Product Obsolete or Under Obsolescence
.
.
.
1,000 to 1,500
K
.
.
.
XC3020A
XC3020L
XC3120A
14,779
14,819
(8 x 8)
256
197
16
64
64
75
9
4) where K is a function of DONE and RESET timing selected. An additional 8 is
—Dummy Bits*
—Preamble Code
—Configuration Program Length
—Dummy Bits (4 Bits Minimum)
Postamble Code (4 Bits Minimum)
1,500 to 2,000
XC3030A
XC3130A
XC3030L
(10 x 10)
22,176
22,216
100
360
241
80
20
11
92
For XC3120
197 Configuration Data Frames
(Each Frame Consists of:
A Start Bit (0)
A 71-Bit Data Field
Three Stop Bits
2,000 to 3,000
generated by the development system begins with a pre-
amble of 111111110010 followed by a 24-bit length count
representing the total number of configuration clocks
needed to complete loading of the configuration pro-
gram(s). The data framing is shown in
FPGAs connected in series read and shift preamble and
length count in on positive and out on negative configura-
tion clock edges. A device which has received the pream-
ble and length count then presents a High Data Out until it
has intercepted the appropriate number of data frames.
When the configuration program memory of an FPGA is full
and the length count does not yet compare, the device
shifts any additional data through, as it did for preamble
and length count. When the FPGA configuration memory is
full and the length count compares, the device will execute
XC3042A
XC3142A
XC3042L
XC3142L
(12 x 12)
30,784
30,824
144
480
108
285
96
24
13
3,500 to 4,500
XC3064A
XC3164A
XC3064L
(16 x 14)
46,064
46,104
224
120
688
140
329
32
15
Header
Program Data
Repeated for Each Logic
Cell Array in a Daisy Chain
November 9, 1998 (Version 3.1)
5,000 to 6,000
XC3090A
XC3190A
XC3090L
XC3190L
(20 x 16)
64,160
64,200
320
144
928
172
373
40
17
X5300_01
6,500 to 7,500
Figure
XC3195A
(22 x 22)
94,944
94,984
1,320
484
176
188
505
44
23
21. All
R