XC3190A-3PQ160C Xilinx Inc, XC3190A-3PQ160C Datasheet - Page 37
![no-image](/images/no-image-200.jpg)
XC3190A-3PQ160C
Manufacturer Part Number
XC3190A-3PQ160C
Description
IC LOGIC CL ARRAY 9000GAT 160PQF
Manufacturer
Xilinx Inc
Series
XC3000A/Lr
Datasheet
1.XC3190A-3PC84C.pdf
(76 pages)
Specifications of XC3190A-3PQ160C
Number Of Labs/clbs
320
Total Ram Bits
64160
Number Of I /o
138
Number Of Gates
6000
Voltage - Supply
4.25 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
160-BQFP
Dc
9929
Case
QFP160
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Logic Elements/cells
-
Other names
122-1047
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3190A-3PQ160C
Manufacturer:
XILINX
Quantity:
455
Part Number:
XC3190A-3PQ160C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
AND of several slave mode devices, a hold-off signal for a
master mode device. After configuration this pin becomes a
user-programmable I/O pin.
BCLKIN
This is a direct CMOS level input to the alternate clock
buffer (Auxiliary Buffer) in the lower right corner.
XTL1
This user I/O pin can be used to operate as the output of an
amplifier driving an external crystal and bias circuitry.
XTL2
This user I/O pin can be used as the input of an amplifier
connected to an external crystal and bias circuitry. The I/O
Block is left unconfigured. The oscillator configuration is
activated by routing a net from the oscillator buffer symbol
output and by the MakeBits program.
CS0, CS1, CS2, WS
These four inputs represent a set of signals, three active
Low and one active High, that are used to control configu-
ration-data entry in the Peripheral mode. Simultaneous
assertion of all four inputs generates a Write to the internal
data buffer. The removal of any assertion clocks in the
D0-D7 data. In Master-Parallel mode, WS and CS2 are the
A0 and A1 outputs. After configuration, these pins are
user-programmable I/O pins.
RDY/BUSY
During Peripheral Parallel mode configuration this pin indi-
cates when the chip is ready for another byte of data to be
written to it. After configuration is complete, this pin
becomes a user-programmed I/O pin.
RCLK
During Master Parallel mode configuration, each change
on the A0-15 outputs is preceded by a rising edge on
RCLK, a redundant output signal. After configuration is
complete, this pin becomes a user-programmed I/O pin.
Note:
pull-up resistor.
November 9, 1998 (Version 3.1)
Before and during configuration, all outputs that are not used for the configuration process are 3-stated with a weak
R
Product Obsolete or Under Obsolescence
XC3000 Series Field Programmable Gate Arrays
Unrestricted User I/O Pins
I/O
An I/O pin may be programmed by the user to be an Input
or an Output pin following configuration. All unrestricted I/O
pins, plus the special pins mentioned on the following page,
have a weak pull-up resistor that becomes active as soon
as the device powers up, and stays active until the end of
configuration.
D0-D7
This set of eight pins represents the parallel configuration
byte for the parallel Master and Peripheral modes. After
configuration is complete, they are user-programmed I/O
pins.
A0-A15
During Master Parallel mode, these 16 pins present an
address output for a configuration EPROM. After configura-
tion, they are user-programmable I/O pins.
DIN
During Slave or Master Serial configuration, this pin is used
as a serial-data input. In the Master or Peripheral configu-
ration, this is the Data 0 input. After configuration is com-
plete, this pin becomes a user-programmed I/O pin.
DOUT
During configuration this pin is used to output serial-config-
uration data to the DIN pin of a daisy-chained slave. After
configuration is complete, this pin becomes a user-pro-
grammed I/O pin.
TCLKIN
This is a direct CMOS-level input to the global clock buffer.
This pin can also be configured as a user programmable
I/O pin. However, since TCLKIN is the preferred input to the
global clock net, and the global clock net should be used as
the primary clock source, this pin is usually the clock input
to the chip.
7-39
7