XC3190A-3PQ160C Xilinx Inc, XC3190A-3PQ160C Datasheet - Page 5
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XC3190A-3PQ160C
Manufacturer Part Number
XC3190A-3PQ160C
Description
IC LOGIC CL ARRAY 9000GAT 160PQF
Manufacturer
Xilinx Inc
Series
XC3000A/Lr
Datasheet
1.XC3190A-3PC84C.pdf
(76 pages)
Specifications of XC3190A-3PQ160C
Number Of Labs/clbs
320
Total Ram Bits
64160
Number Of I /o
138
Number Of Gates
6000
Voltage - Supply
4.25 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
160-BQFP
Dc
9929
Case
QFP160
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Logic Elements/cells
-
Other names
122-1047
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3190A-3PQ160C
Manufacturer:
XILINX
Quantity:
455
Part Number:
XC3190A-3PQ160C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Figure 3: Static Configuration Memory Cell.
It is loaded with one bit of configuration program and con-
trols one program selection in the Field Programmable
Gate Array.
The memory cell outputs Q and Q use ground and V
els and provide continuous, direct control. The additional
capacitive load together with the absence of address
decoding and sense amplifiers provide high stability to the
cell. Due to the structure of the configuration memory cells,
they are not affected by extreme power-supply excursions
or very high levels of alpha particle radiation. In reliability
November 9, 1998 (Version 3.1)
Read or
Figure 4: Input/Output Block.
Each IOB includes input and output storage elements and I/O options selected by configuration memory cells. A choice
of two clocks is available on each die edge. The polarity of each clock line (not each flip-flop or latch) is programmable.
A clock line that triggers the flip-flop on the rising edge is an active Low Latch Enable (Latch transparent) signal and vice
versa. Passive pull-up can only be enabled on inputs, not on outputs. All user inputs are programmed for TTL or CMOS
thresholds.
Write
Data
(OUTPUT ENABLE)
REGISTERED IN
R
DIRECT IN
3- STATE
OUT
PROGRAM
CONTROLLED
MULTIPLEXER
Product Obsolete or Under Obsolescence
T
O
I
Q
INVERT
OUT
OK
Q
Q
PROGRAM-CONTROLLED MEMORY CELLS
Configuration
Control
3-STATE
INVERT
IK
=
X5382
CC
PROGRAMMABLE INTERCONNECTION POINT or PIP
LATCH
D
Q
FLOP
FLOP
FLIP
FLIP
R
or
R
lev-
Q
D
XC3000 Series Field Programmable Gate Arrays
OUTPUT
SELECT
testing, no soft errors have been observed even in the
presence of very high doses of alpha radiation.
The method of loading the configuration data is selectable.
Two methods use serial data, while three use byte-wide
data. The internal configuration logic utilizes framing infor-
mation, embedded in the program data by the development
system, to direct memory-cell loading. The serial-data
framing and length-count preamble provide programming
compatibility for mixes of various FPGA device devices in a
synchronous, serial, daisy-chain fashion.
I/O Block
Each user-configurable IOB shown in
interface between the external package pin of the device
and the internal user logic. Each IOB includes both regis-
tered and direct input paths. Each IOB provides a program-
mable 3-state output buffer, which may be driven by a
registered or direct output signal. Configuration options
allow each IOB an inversion, a controlled slew rate and a
high impedance pull-up. Each input circuit also provides
input clamping diodes to provide electrostatic protection,
and circuits to inhibit latch-up produced by input currents.
THRESHOLD
TTL or
CMOS
INPUT
SLEW
RATE
OUTPUT
BUFFER
PASSIVE
PULL UP
(GLOBAL RESET)
CK1
CK2
Vcc
Figure
I/O PAD
X3029
4, provides an
7-7
7