AN2131QC Cypress Semiconductor Corp, AN2131QC Datasheet - Page 105

• Manufacturer Part Number: AN2131QC
• Description: IC MCU 8051 8K RAM 24MHZ 80BQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB®r

Specifications of AN2131QC

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: AN213x
• Ram Size: 8K x 8
• Interface: I²C, USB
• Number Of I /o: 24
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1307

host issues a NAK, indicating busy (6). The data at (5) is shaded to indicate that the USB
core discards it, and does not over-write the data in the endpoint’s OUT buffer.
The host continues to send OUT tokens (4, 5, and 6) that are greeted by NAKs until the
buffer is ready. Eventually, the 8051 empties the endpoint buffer data, and then loads the
endpoint’s byte count register (7) with any value to re-arm the USB core. Once armed and
when the next OUT token arrives (8) the USB core accepts the next data packet (9).
The EZ-USB core takes care of USB housekeeping chores such as CRC checks and data
toggle PIDs. When an endpoint 6-OUT interrupt occurs and the busy bit is cleared, the
user is assured that the data in the endpoint buffer was received error-free from the host.
The EZ-USB core automatically checks for errors and requests the host to re-transmit data
if it detects any errors using the built-in USB error checking mechanisms (CRC checks
and data toggles).
The 8051 sets endpoint pairing bits to 1 to enable double-buffering of the bulk endpoint
buffers. With double buffering enabled, the 8051 can operate on one data packet while
another is being transferred over USB. The endpoint busy and interrupt request bits func-
tion identically, so the 8051 code requires little code modification to support double-buff-
ering.
When an endpoint is paired, the 8051 uses only the even-numbered endpoint of the pair.
The 8051 should not use the paired odd endpoint. For example, suppose it is desired to
Page 6-8
Initializing OUT Endpoints
When the EZ-USB chip comes out of reset, or when the USB host issues a bus reset, the
EZ-USB core arms OUT endpoints 1-7 by setting their busy bits to 1. Therefore, they
are initially ready to accept one OUT transfer from the host. Subsequent OUT transfers
are NAKd until the appropriate OUTnBC register is loaded to re-arm the endpoint.
6.6
Endpoint Pairing
Bit
Name
Paired
Endpoints
Table 6-2. Endpoint Pairing Bits (in the USB PAIR Register)
PR6OUT
6 OUT
7 OUT
5
PR4OUT
4 OUT
5 OUT
Chapter 6. EZ-USB CPU
4
PR2OUT
2 OUT
3 OUT
3
PR6IN
6 IN
7 IN
2
PR4IN
4 IN
5 IN
1
PR2IN
2 IN
3 IN
0
EZ-USB TRM v1.9