AN2131QC Cypress Semiconductor Corp, AN2131QC Datasheet - Page 70

• Manufacturer Part Number: AN2131QC
• Description: IC MCU 8051 8K RAM 24MHZ 80BQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB®r

Specifications of AN2131QC

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: AN213x
• Ram Size: 8K x 8
• Interface: I²C, USB
• Number Of I /o: 24
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1307

or I2DAT until the STOP bit returns low. In the 2122/2126 only, an interrupt request is
available to signal that STOP bit transmission is complete.
4.6.3 LASTRD
To read data over the I
the SCL line. After every eight bits, the master drives SDA low for one clock to indicate
ACK. To signal the last byte of the read transfer, the master floats SDA at ACK time to
instruct the slave to stop sending. This is controlled by the 8051 by setting LASTRD=1
before reading the last byte of a read transfer. The I
the end of the transfer (at ACK time).
After a byte transfer the EZ-USB controller updates the three status bits BERR, ACK, and
DONE. If no STOP condition was transmitted, they are updated at ACK time. If a STOP
condition was transmitted they are updated after the STOP condition is transmitted.
4.7.1 DONE
The I
stage. The controller also generates an I
DONE bit. The I
I2DAT register, and the I
I2CS or I2DAT register.
4.7.2 ACK
Every ninth SCL of a write transfer, the slave indicates reception of the byte by asserting
ACK. The EZ-USB controller floats SDA during this time, samples the SDA line, and
updates the ACK bit with the complement of the detected value. ACK=1 indicates
acknowledge, and ACK=0 indicates not-acknowledge. The EZ-USB core updates the
EZ-USB TRM v1.9
Note
Setting LASTRD does not automatically generate a STOP condition. The 8051 should
also set the STOP bit at the end of a read transfer.
4.7
2
C controller sets this bit whenever it completes a byte transfer, right after the ACK
Status Bits
2
C controller clears the DONE bit when the 8051 reads or writes the
2
C bus, an I
2
C interrupt request bit whenever the 8051 reads or writes the
2
C master floats the SDA line and issues clock pulses on
Chapter 4. EZ-USB CPU
2
C interrupt request (8051 INT3) when it sets the
2
C controller clears the LASTRD bit at
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