CY7C63001C-SXC Cypress Semiconductor Corp, CY7C63001C-SXC Datasheet - Page 12

• Manufacturer Part Number: CY7C63001C-SXC
• Description: IC MCU 4K USB MCU LS 20SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C63001C-SXC

• Applications: USB Microcontroller
• Core Processor: M8A
• Program Memory Type: OTP (4 kB)
• Controller Series: CY7C630xx
• Ram Size: 128 x 8
• Interface: USB
• Number Of I /o: 12
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1850

Document #: 38-08026 Rev. *B
The Program Counter (PC) value and the Carry and Zero flags
(CF, ZF) are automatically stored onto the Program Stack by
the CALL instruction as part of the interrupt acknowledge
process. The user firmware is responsible for ensuring that the
processor state is preserved and restored during an interrupt.
For example the PUSH A instruction should be used as the
first command in the ISR to save the accumulator value. And,
the IPRET instruction should be used to exit the ISR with the
accumulator value restored and interrupts enabled. The PC,
CF, and ZF are restored when the IPRET or RET instructions
are executed.
The Interrupt Vectors supported by the USB Controller are
listed in Table 6-3. Interrupt Vector 0 (Reset) has the highest
priority, Interrupt Vector 7 has the lowest priority. Because the
JMP instruction is 2 bytes long, the interrupt vectors occupy 2
bytes.
6.8.1
Interrupt latency can be calculated from the following
equation:
Interrupt Latency = (Number of clock cycles remaining in the
For example, if a 5-clock-cycle instruction such as JC is being
executed when an interrupt occurs, the first instruction of the
Interrupt Service Routine executes a minimum of 16 clock
cycles (1+10+5) or a maximum of 20 clock cycles (5+10+5)
after the interrupt is issued. Therefore, the interrupt latency in
this example will be = 20 clock periods = 20 / (12 MHz) =
Table 6-3. Interrupt Vector Assignments
IE0.7
IE1.7
b7
b7
W
W
0
0
Interrupt Latency
Interrupt Priority
0 (Highest)
7 (Lowest)
1
2
3
4
5
6
current instruction) + (10 clock cycles for
the CALL instruction) + (5 clock cycles
for the JMP instruction)
IE0.6
IE1.6
b6
b6
W
W
0
0
Figure 6-14. Port 0 Interrupt Enable Register (P0 IE - Address 0x04)
Figure 6-15. Port 1 Interrupt Enable Register (P1 IE - Address 0x05)
IE0.5
IE1.5
b5
b5
W
W
0
0
ROM Address
IE0.4
IE1.4
b4
b4
W
W
0
0
0x0A
0x0C
0x0E
0x00
0x02
0x04
0x06
0x08
1.667 µs. The interrupt latches are sampled at the rising edge
of the last clock cycle in the current instruction.
6.8.2
The General Purpose I/O interrupts are generated by signal
transitions at the Port 0 and Port 1 I/O pins. GPIO interrupts
are edge sensitive with programmable interrupt polarities.
Setting a bit HIGH in the Port Pull-up Register (see
Figure 6-10 and 6-11) selects a LOW to HIGH interrupt trigger
for the corresponding port pin. Setting a bit LOW activates a
HIGH to LOW interrupt trigger. Each GPIO interrupt is
maskable on a per-pin basis by a dedicated bit in the Port
Interrupt Enable Register. Writing a “1” enables the interrupt.
Figure 6-14 and Figure 6-15 illustrate the format of the Port
Interrupt Enable Registers for Port 0 and Port 1 located at I/O
address 0x04 and 0x05 respectively. These write only
registers are cleared during reset, thus disabling all GPIO
interrupts.
A block diagram of the GPIO interrupt logic is shown in
Figure 6-16. The bit setting in the Port Pull-up Register selects
the interrupt polarity. If the selected signal polarity is detected
on the I/O pin, a HIGH signal is generated. If the Port Interrupt
Enable bit for this pin is HIGH and no other port pins are
requesting interrupts, the OR gate issues a LOW to HIGH
signal to clock the GPIO interrupt flip-flop. The output of the
flip-flop is further qualified by the Global GPIO Interrupt Enable
bit before it is processed by the Interrupt Priority Encoder. Both
the GPIO interrupt flip-flop and the Global GPIO Enable bit are
cleared
acknowledge.
IE0.3
IE1.3
b3
b3
W
W
0
0
GPIO Interrupt
by
Reset
128-µs timer interrupt
1.024-ms timer interrupt
USB endpoint 0 interrupt
USB endpoint 1 interrupt
Reserved
GPIO interrupt
Wake-up interrupt
on-chip hardware during
IE0.2
IE1.2
b2
b2
W
W
0
0
Function
IE0.1
IE1.1
b1
b1
W
W
0
0
CY7C63001C
CY7C63101C
GPIO interrupt
Page 12 of 28
IE0.0
IE1.0
b0
b0
W
W
0
0