CY7C63001C-SXC Cypress Semiconductor Corp, CY7C63001C-SXC Datasheet - Page 15

• Manufacturer Part Number: CY7C63001C-SXC
• Description: IC MCU 4K USB MCU LS 20SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C63001C-SXC

• Applications: USB Microcontroller
• Core Processor: M8A
• Program Memory Type: OTP (4 kB)
• Controller Series: CY7C630xx
• Ram Size: 128 x 8
• Interface: USB
• Number Of I /o: 12
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1850

Document #: 38-08026 Rev. *B
A maximum of 8 bytes are written into the Endpoint 0 FIFO. If
there are less than 8 bytes of data the CRC is written into the
FIFO.
Due to register space limitations, the Receive Data Invalid bit
is located in the USB Endpoint 0 TX Configuration Register.
Refer to the Endpoint 0 Transmit section for details. This bit is
set by the SIE if an error is detected in a received DATA packet.
Table 6-4 summarizes the USB Engine response to SETUP
and OUT transactions on Endpoint 0. In the Data Packet
column ‘Error’ represents a packet with a CRC, PID or
bit-stuffing error, or a packet with more than 8 bytes of data.
‘Valid’ is a packet without an Error. ‘Status’ is a packet that is
a valid control read Status stage, while ‘N/Status’ is not a
correct Status stage (see section 6.9.4). The ‘Stall’ bit is
described
‘EnableOuts’ bits are described in section 6.9.4.
6.9.2.2 Endpoint 0 Transmit
The USB Endpoint 0 TX Register located at I/O address 0x10
controls data transmission from Endpoint 0 (see Figure 6-19).
This is a read/write register. All bits are cleared during reset.
Bits 0 to 3 indicate the numbers of data bytes to be transmitted
during an IN packet, valid values are 0 to 8 inclusive. Bit 4
indicates that a received DATA packet error (CRC, PID, or
Table 6-4. USB Engine Response to SETUP and OUT Transactions on Endpoint 0
Stall
INEN
INEN
0
0
0
0
1
1
0
0
0
R/W
R/W
-
-
b7
b7
0
0
Control Bit Settings
in
Status Out
Section
0
0
0
0
0
0
1
1
1
-
-
DATA1/0
DATA1/0
R/W
R/W
b6
b6
0
0
Figure 6-19. USB Endpoint 0 TX Configuration Register (Address 0x10)
Figure 6-20. USB Endpoint 1 TX Configuration Register (Address 0x11)
6.9.2.2.
Enable
Out
1
1
0
0
0
0
0
0
0
-
-
STALL
STALL
The
R/W
R/W
b5
b5
0
0
SETUP
SETUP
Received Packets
Token
Type
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
‘StatusOuts’
EP1EN
N/Status
ERR
R/W
R/W
Packet
Status
b4
b4
Data
Valid
Error
Valid
Error
Valid
Error
Valid
Error
Error
0
0
and
FIFO Write
bitstuffing error) occurred during a SETUP or OUT data phase.
Setting the Stall bit (bit 5) stalls IN and OUT packets. This bit
is cleared whenever a SETUP packet is received by
Endpoint 0. Bit 6 (Data 1/0) must be set to 0 or 1 to select the
DATA packet’s toggle state (0 for DATA0, 1 for DATA1).
After the transmit data has been loaded into the FIFO, bit 6
should be set according to the data toggle state and bit 7 set
to “1”. This enables the USB Controller to respond to an IN
packet. Bit 7 is cleared and an Endpoint 0 interrupt is
generated by the SIE once the host acknowledges the data
transmission. Bit 7 is also cleared when a SETUP token is
received. The Interrupt Service Routine can check bit 7 to
confirm that the data transfer was successful.
6.9.3
Endpoint 1 is capable of transmit only. The data to be trans-
mitted is stored in the 8-byte Endpoint 1 FIFO located at data
memory space 0x78 to 0x7F.
6.9.3.1 Endpoint 1 Transmit
Transmission is controlled by the USB Endpoint 1 TX Register
located at I/O address 0x11 (see Figure 6-20). This is a
read/write register. All bits are cleared during reset.
COUNT3
COUNT3
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
R/W
R/W
b3
b3
0
0
Endpoint 1
Update
Toggle
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
COUNT2
COUNT2
USB Engine Response
R/W
R/W
b2
b2
0
0
Update
Count
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
COUNT1
COUNT1
R/W
R/W
b1
b1
0
0
Interrupt
CY7C63001C
CY7C63101C
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
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COUNT0
COUNT0
R/W
R/W
STALL
STALL
Reply
b0
None
None
None
None
None
b0
ACK
ACK
NAK
ACK
0
0