CY7C63001C-SXC Cypress Semiconductor Corp, CY7C63001C-SXC Datasheet - Page 13

• Manufacturer Part Number: CY7C63001C-SXC
• Description: IC MCU 4K USB MCU LS 20SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C63001C-SXC

• Applications: USB Microcontroller
• Core Processor: M8A
• Program Memory Type: OTP (4 kB)
• Controller Series: CY7C630xx
• Ram Size: 128 x 8
• Interface: USB
• Number Of I /o: 12
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1850

Document #: 38-08026 Rev. *B
Note: If one port pin triggers an interrupt, no other port pin can
cause a GPIO interrupt until the port pin that triggered the
interrupt has returned to its inactive (non-trigger) state or until
its corresponding port interrupt enable bit is cleared (these
events ‘reset’ the clock of the GPIO Interrupt flip-flop, which
must be ‘reset’ to ‘0’ before another GPIO interrupt event can
‘clock’ the GPIO Interrupt flip-flop and produce an IRQ).
Note: If the port pin that triggered an interrupt is held in its
active (trigger) state while its corresponding port interrupt
enable bit is cleared and then set, a GPIO interrupt event
occurs as the GPIO Interrupt flip-flop clock transitions from ‘1’
to ‘0’ and then back to ‘1’ (please refer to Figure 6-16). The
USB Controller does not assign interrupt priority to different
port pins and the Port Interrupt Enable Registers are not
cleared during the interrupt acknowledge process. When a
GPIO interrupt is serviced, the ISR must poll the ports to
determine which pin caused the interrupt.
6.8.3
A USB Endpoint 0 interrupt is generated after the host has
written data to Endpoint 0 or after the USB Controller has
transmitted a packet from Endpoint 0 and receives an ACK
from the host. An OUT packet from the host which is NAKed
by the USB Controller does not generate an interrupt. This
interrupt is masked by the USB EP0 Interrupt Enable bit (bit 3)
of the Global Interrupt Enable Register.
A USB Endpoint 1 interrupt is generated after the USB
Controller has transmitted a packet from Endpoint 1 and has
received an ACK from the host. This interrupt is masked by the
USB EP1 Interrupt Enable bit (bit 4) of the Global Interrupt
Enable Register.
6.8.4
There are two timer interrupts: the 128-µs interrupt and the
1.024-ms interrupt. They are masked by bits 1 and 2 of the
Global Interrupt Enable Register respectively. The user should
disable both timer interrupts before going into the suspend
GPIO
Pin
1 = Enable
0 = Disable
USB Interrupt
Timer Interrupt
Acknowledge
Interrupt
Port Interrupt
Enable Register
1 = Enable
0 = Disable
Port
Pull-Up
Register
M
U
X
Figure 6-16. GPIO Interrupt Logic Block Diagram
(Bit 6, Register 0x20)
GPIO Interrupt
1=L
0=H
Global
Enable
→
→
CLR
H
L
(1 input per
OR Gate
GPIO pin)
mode to avoid possible conflicts from timer interrupts occurring
just as suspend mode is entered.
6.8.5
A wake-up interrupt is generated when the Cext pin goes
HIGH. This interrupt is latched in the interrupt controller. It can
be masked by the Wake-up Interrupt Enable bit (bit 7) of the
Global Interrupt Enable Register. This interrupt can be used to
perform periodic checks on attached peripherals when the
USB Controller is placed in the low-power suspend mode. See
the Instant-On Feature section for more details.
6.9
The USB engine includes the Serial Interface Engine (SIE)
and the low-speed USB I/O transceivers. The SIE block
performs most of the USB interface functions with only minimal
support from the microcontroller core. Two endpoints are
supported. Endpoint 0 is used to receive and transmit control
(including setup) packets while Endpoint 1 is only used to
transmit data packets.
The USB SIE processes USB bus activity at the transaction
level independently. It does all the NRZI encoding/decoding
and bit stuffing/unstuffing. It also determines token type,
checks address and endpoint values, generates and checks
CRC values, and controls the flow of data bytes between the
bus and the Endpoint FIFOs. NOTE: the SIE stalls the CPU for
3 cycles per byte when writing data to the endpoint FIFOs (or
3 * 1/12 MHz * 8 bytes = 2 µs per 8-byte transfer).
The firmware handles higher level and function-specific tasks.
During control transfers the firmware must interpret device
requests and respond correctly. It also must coordinate
Suspend/Resume, verify and select DATA toggle values, and
perform function specific tasks.
The USB engine and the firmware communicate though the
Endpoint FIFOs, USB Endpoint interrupts, and the USB
registers described in the sections below.
Wake-Up Interrupt
USB Engine
I
GPIO Interrupt
Flip-Flop
D
CLR
Interrupt
Q
Encoder
Priority
CY7C63001C
CY7C63101C
Interrupt
IRQ
Vector
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