CY7C64714-100AXC Cypress Semiconductor Corp, CY7C64714-100AXC Datasheet
CY7C64714-100AXC
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CY7C64714-100AXC Summary of contents
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... D– XCVR Integrated full-speed XCVR Enhanced USB core Simplifies 8051 code Cypress Semiconductor Corporation Document #: 38-08039 Rev. *C EZ-USB FX1™ USB Microcontroller Full-speed USB Peripheral Controller — Supports multiple Ready (RDY) inputs and Control (CTL) outputs • Integrated, industry standard 8051 with enhanced features — ...
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Functional Description EZ-USB FX1 (CY7C64713/ full-speed highly integrated, USB microcontroller. By integrating the USB trans- ceiver, serial interface engine (SIE), enhanced 8051 microcon- troller, and a programmable peripheral interface in a single chip, Cypress has created a ...
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Table 4-1. Special Function Registers IOA IOB 1 SP EXIF 2 DPL0 MPAGE 3 DPH0 4 DPL1 5 DPH1 6 DPS 7 PCON 8 TCON SCON0 9 TMOD SBUF0 A TL0 AUTOPTRH1 B TL1 AUTOPTRL1 C ...
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USB-Interrupt Autovectors The main USB interrupt is shared by 27 interrupt sources. To save the code and processing time that normally would be required to identify the individual USB interrupt source, the FX1 provides a second level of interrupt ...
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Table 4-4. Individual FIFO/GPIF Interrupt Sources Priority INT4VEC Value Autovectoring is ...
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Table 4-5. Reset Timing Values Condition Power-On Reset with crystal Power-On Reset with external 200 s + Clock stability time clock Powered Reset 4.9.2 Wakeup Pins The 8051 puts itself and the rest of the chip into a power-down mode ...
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FFFF E200 E1FF E000 3FFF 0000 *SUDPTR, USB upload/download, I 4.11 Register Addresses Document #: 38-08039 Rev. *C Inside FX1 Outside FX1 7.5 KBytes (OK to populate USB regs and data memory 4K FIFO buffers here—RD#/WR# (RD#,WR#) strobes are not ...
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Endpoint RAM 4.12.1 Size • 3 × 64 bytes (Endpoints 0 and 1) • 8 × 512 bytes (Endpoints 4.12.2 Organization • EP0—Bidirectional endpoint zero, 64-byte buffer • EP1IN, EP1OUT—64-byte buffers, bulk or interrupt • ...
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FIFOS” and “Slave FIFOS.” Since they are physically the same memory, no bytes are actually transferred between buffers. At any given time, some RAM blocks are filling/emptying with USB data under SIE ...
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Write any value to ECCRESET then pass data across the GPIF or Slave FIFO interface. The ECC for the first 512 bytes of data will be calculated and stored in ECC1; ECC2 is unused. After the ECC is calculated, the ...
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Document #: 38-08039 Rev. *C Port GPIF Master PD7 FD[15] PD6 FD[14] PD5 FD[13] PD4 FD[12] PD3 FD[11] PD2 FD[10] PD1 FD[9] PD0 FD[8] PB7 FD[7] PB6 FD[6] PB5 FD[5] XTALIN FD[4] PB4 XTALOUT PB3 FD[3] RESET# PB2 FD[2] WAKEUP# ...
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CLKOUT 1 VCC 2 3 GND 4 RDY0/*SLRD 5 RDY1/*SLWR 6 RDY2 7 RDY3 RDY4 8 RDY5 9 AVCC 10 XTALOUT 11 XTALIN 12 AGND AVCC 18 DPLUS 19 DMINUS AGND 20 ...
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VCC 1 GND 2 RDY0/*SLRD 3 RDY1/*SLWR 4 RDY2 5 RDY3 6 RDY4 7 RDY5 8 AVCC 9 XTALOUT 10 XTALIN 11 AGND AVCC 16 DPLUS 17 DMINUS 18 AGND 19 VCC 20 ...
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RDY0/*SLRD 1 RDY1/*SLWR 2 AVCC 3 XTALOUT 4 XTALIN 5 AGND 6 AVCC 7 DPLUS 8 DMINUS 9 AGND 10 VCC 11 GND 12 *IFCLK/**PE0/T0OUT 13 RESERVED 14 Figure 5-4. CY7C64713/4 56-pin QFN Pin Assignment Document #: 38-08039 Rev. *C ...
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CY7C64713/4 Pin Definitions [8] Table 5-1. FX1 Pin Definitions 128 100 56 TQFP TQFP QFN Name Type AVCC Power AVCC Power AGND Ground AGND Ground 19 18 ...
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Table 5-1. FX1 Pin Definitions (continued) 128 100 56 TQFP TQFP QFN Name Type RESET# Input 35 EA Input XTALIN Input XTALOUT Output 1 100 54 CLKOUT O/Z Port A 82 ...
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Table 5-1. FX1 Pin Definitions (continued) 128 100 56 TQFP TQFP QFN Name Type PA7 or I/O/Z FLAGD or SLCS# Port PB0 or I/O/Z FD[ PB1 or I/O/Z FD[1] 46 ...
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Table 5-1. FX1 Pin Definitions (continued) 128 100 56 TQFP TQFP QFN Name Type 77 62 PC5 or I/O/Z GPIFADR5 78 63 PC6 or I/O/Z GPIFADR6 79 64 PC7 or I/O/Z GPIFADR7 PORT D 102 80 45 PD0 or I/O/Z ...
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Table 5-1. FX1 Pin Definitions (continued) 128 100 56 TQFP TQFP QFN Name Type 111 89 PE3 or I/O/Z RXD0OUT 112 90 PE4 or I/O/Z RXD1OUT 113 91 PE5 or I/O/Z INT6 114 92 PE6 or I/O/Z T2EX 115 93 ...
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Table 5-1. FX1 Pin Definitions (continued) 128 100 56 TQFP TQFP QFN Name Type IFCLK I/O INT4 Input 106 84 INT5# Input Input Input Input 53 ...
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Table 5-1. FX1 Pin Definitions (continued) 128 100 56 TQFP TQFP QFN Name Type GND Ground GND Ground 49 39 GND Ground GND Ground GND Ground 80 65 ...
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Register Summary FX1 register bit definitions are described in the EZ-USB TRM in greater detail. Table 6-1. FX1 Register Summary Hex Size Name Description GPIF Waveform Memories E400 128 WAVEDATA GPIF Waveform Descriptor data E480 ...
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Table 6-1. FX1 Register Summary (continued) Hex Size Name Description E62F 1 ECC2B2 ECC2 Byte 2 Address [9] E630 1 EP2FIFOPFH Endpoint 2 / slave FIFO Programmable Flag H ISO Mode [9] E630 1 EP2FIFOPFH Endpoint 2 / slave FIFO ...
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Table 6-1. FX1 Register Summary (continued) Hex Size Name Description [10] E659 1 IBNIRQ IN-BULK-NAK interrupt Request E65A 1 NAKIE Endpoint Ping-NAK / IBN Interrupt Enable [10] E65B 1 NAKIRQ Endpoint Ping-NAK / IBN Interrupt Request E65C 1 USBIE USB ...
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Table 6-1. FX1 Register Summary (continued) Hex Size Name Description [9] E698 1 EP6BCH Endpoint 6 Byte Count H 0 [9] E699 1 EP6BCL Endpoint 6 Byte Count L BC7/SKIP E69A 2 reserved [9] E69C 1 EP8BCH Endpoint 8 Byte ...
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Table 6-1. FX1 Register Summary (continued) Hex Size Name Description E6CB 1 FLOWSTB Flowstate Strobe Configuration E6CC 1 FLOWSTBEDGE Flowstate Rising/Falling Edge Configuration E6CD 1 FLOWSTBPERIOD Master-Strobe Half-Period D7 [9] E6CE 1 GPIFTCB3 GPIF Transaction Count Byte 3 [9] E6CF ...
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Table 6-1. FX1 Register Summary (continued) Hex Size Name Description Stack Pointer 82 1 DPL0 Data Pointer DPH0 Data Pointer 0 H [10 DPL1 Data Pointer 1 L [10 ...
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Table 6-1. FX1 Register Summary (continued) Hex Size Name Description C8 1 T2CON Timer/Counter 2 Control (bit addressable reserved CA 1 RCAP2L Capture for Timer 2, auto- reload, up-counter CB 1 RCAP2H Capture for Timer 2, auto- reload, ...
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... OL I Output Current HIGH OH I Output Current LOW OL C Input Pin Capacitance IN I Suspend Current SUSP CY7C64714 Suspend Current CY7C64713 I Supply Current CC T Reset Time after Valid Power RESET Pin Reset after powered on 9.1 USB Transceiver USB 2.0-compliant in full-speed mode. Note: 12 recommended to not power I/O when chip power is off. 13. Measured at Max VCC, 25º ...
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AC Electrical Characteristics 10.1 USB Transceiver USB 2.0-compliant in full-speed mode. 10.2 Program Memory Read t CL [14] CLKOUT t AV A[15..0] PSEN# D[7..0] t SOEL OE# t SCSL CS# Figure 10-1. Program Memory Read Timing Diagram Table 10-1. ...
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Data Memory Read t CL [14] CLKOUT t AV A[15..0] RD# CS# OE# D[7.. [14] CLKOUT t AV A[15..0] RD# CS# D[7..0] Table 10-2. Data Memory Read Parameters Parameter Description t 1/CLKOUT Frequency CL t Delay from ...
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Data Memory Write t CL CLKOUT t AV A[15..0] WR# t SCSL CS# t ON1 D[7.. CLKOUT t AV A[15..0] WR# CS# t ON1 D[7..0] Table 10-3. Data Memory Write Parameters Parameter t Delay from Clock to ...
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PORTC Strobe Feature Timings The RD# and WR# are present in the 100-pin version and the 128-pin package. In these 100-pin and 128-pin versions, an 8051 control bit can be set to pulse the RD# and WR# pins when ...
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GPIF Synchronous Signals IFCLK GPIFADR[8:0] RDY DATA(input) CTL DATA(output) Figure 10-6. GPIF Synchronous Signals Timing Diagram Table 10-4. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK Parameter t IFCLK Period IFCLK t RDY to Clock Setup Time SRY X ...
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Slave FIFO Synchronous Read IFCLK SLRD FLAGS DATA SLOE Figure 10-7. Slave FIFO Synchronous Read Timing Diagram Table 10-6. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK Parameter t IFCLK Period IFCLK t SLRD to Clock Setup Time ...
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Slave FIFO Asynchronous Read SLRD FLAGS DATA SLOE Figure 10-8. Slave FIFO Asynchronous Read Timing Diagram Table 10-8. Slave FIFO Asynchronous Read Parameters Parameter t SLRD Pulse Width LOW RDpwl t SLRD Pulse Width HIGH RDpwh t SLRD to ...
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Slave FIFO Synchronous Write IFCLK SLWR DATA FLAGS Figure 10-9. Slave FIFO Synchronous Write Timing Diagram Table 10-9. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK Parameter t IFCLK Period IFCLK t SLWR to Clock Setup Time SWR ...
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Slave FIFO Asynchronous Write SLWR/SLCS# DATA FLAGS Figure 10-10. Slave FIFO Asynchronous Write Timing Diagram Table 10-11. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK Parameter t SLWR Pulse LOW WRpwl t SLWR Pulse HIGH WRpwh t SLWR ...
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A full packet (full defined as the number of bytes in the FIFO meeting the level set in AUTOINLEN register) committed automatically ...
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Slave FIFO Output Enable SLOE DATA Figure 10-14. Slave FIFO Output Enable Timing Diagram Table 10-15. Slave FIFO Output Enable Parameters Parameter t SLOE Assert to FIFO DATA Output OEon t SLOE Deassert to FIFO DATA Hold OEoff 10.14 ...
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Slave FIFO Synchronous Address IFCLK SLCS/FIFOADR [1:0] Figure 10-16. Slave FIFO Synchronous Address Timing Diagram Table 10-17. Slave FIFO Synchronous Address Parameters Parameter t Interface Clock Period IFCLK t FIFOADR[1:0] to Clock Setup Time SFA t Clock to FIFOADR[1:0] ...
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Sequence Diagram 10.17.1 Single and Burst Synchronous Read Example t IFCLK IFCLK t SFA FIFOADR t=0 t SRD SLRD t=2 SLCS FLAGS Data Driven: N DATA t OEon SLOE t=1 Figure 10-18. Slave FIFO Synchronous Read Sequence and Timing ...
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Single and Burst Synchronous Write t IFCLK IFCLK t SFA FIFOADR t=0 t SWR SLWR t=2 SLCS FLAGS t SFD N DATA t=1 PKTEND Figure 10-20. Slave FIFO Synchronous Write Sequence and Timing Diagram The Figure 10-20 shows the ...
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Sequence Diagram of a Single and Burst Asynchronous Read t t SFA FAH FIFOADR t RDpwl RDpwh SLRD t=3 t=2 SLCS FLAGS t XFD Data (X) DATA N Driven t OEon SLOE t=4 t=1 Figure 10-21. Slave ...
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... FIFO and then increments the FIFO 11.0 Ordering Information Table 11-1. Ordering Information Ordering Code Ideal for battery powered applications CY7C64714-128AXC 128 TQFP – Lead-Free CY7C64714-100AXC 100 TQFP – Lead-Free CY7C64714-56LFXC 56 QFN – Lead-Free Ideal for non-battery powered applications CY7C64713-128AXC 128 TQFP - Lead-Free CY7C64713-100AXC ...
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Package Diagrams The FX1 is available in three packages: • 56-pin QFN • 100-pin TQFP • 128-pin TQFP Package Diagrams TOP VIEW 7.90[0.311] A 8.10[0.319] 7.70[0.303] 7.80[0.307 0.80[0.031] DIA. Document #: 38-08039 Rev. *C SIDE VIEW ...
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Package Diagrams (continued) Figure 12-2. 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 Document #: 38-08039 Rev. *C CY7C64713/14 51-85050-*A Page ...
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Package Diagrams (continued) Figure 12-3. 128-Lead Thin Plastic Quad Flatpack ( 1.4 mm) A128 13.0 Quad Flat Package No Leads (QFN) Package Design Notes Electrical contact of the part to the Printed Circuit Board (PCB) is made ...
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... Document #: 38-08039 Rev. *C © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...
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... Provided additional timing restrictions and requirement regarding the use of PKTEND pin to commit a short one byte/word packet subsequent to committing a packet automatically (when in auto mode). Added part number CY7C64714 ideal for battery powered applications. Changed Supply Voltage in section 8 to read +3.15V to +3.45V Added Min Vcc Ramp Up time (0 to 3.3v) Removed Preliminary Corrected signal name for pin 54 in Figure 5-4 ...