Z85C3008VSG Zilog, Z85C3008VSG Datasheet - Page 174
Z85C3008VSG
Manufacturer Part Number
Z85C3008VSG
Description
IC 8MHZ Z8500 CMOS SCC 44-PLCC
Manufacturer
Zilog
Series
SCCr
Specifications of Z85C3008VSG
Processor Type
Z80
Features
Error Detection and Multiprotocol Support
Speed
8MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
44-LCC (J-Lead)
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Cpu Speed
8MHz
Digital Ic Case Style
LCC
No. Of Pins
44
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
85
Rohs Compliant
Yes
Clock Frequency
8MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3932
Z85C3008VSG
Z85C3008VSG
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Manufacturer
Quantity
Price
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Part Number:
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Manufacturer:
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Quantity:
800
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Part Number:
Z85C3008VSG
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MAX
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UM010901-0601
I/O Read Cycle
These tables show that a delay of the falling edge of /RD
satisfies the SCC TsA(RD) timing requirement of 50 ns
min. The Z180 calculated value is 30 ns min for the worst
case. Also, Z180 timing specification tAH (Address Hold
time) is 10 ns min. The SCC timing parameters ThA(RD)
{Address to /RD High Hold} and ThCE(RD) {/CE to /RD
High Hold} are minimum at 0 ns. The rising edge of /RD is
early to guarantee these parameters when considering
address decoders and gate propagation delays.
I/O Write Cycle
Delay the falling edge of /WR to satisfy the SCC TsA(/WR)
timing requirement of 50 ns min. The Z180 calculates 30
SCC
Parameters
TsA(RD)
TdA(DR)
TdRDf(DR)
TwRDI
TsA(WR)
TsDW(WR)
TwWRI
Z180
Parameters
tDRS
Table 8. Parameter Equations Worst Case (Without Delay Signals - No Wait State)
Z180
Equation
tcyc-tAD+tRDD1
3tcyc+tCHW+tcf-tAD-tDRS
2tcyc+tCHW+tcf-tRDD1-tDRS
2tcyc+tCHW+tcf-tDRS+tRDD2
tcyc-tAD+tWRD1
tWDS
tWRP
SCC
Equation
Address
3tcyc+tCHW-tAD-TdA(DR)
RD
2tcyc+tCHW-tRDD1-TdRD(DR)
Table 9. Parameter Equations
ns min worst case. Further, the Z180 timing specifications
tAH (Address Hold time) and tWDH (/WR high to data hold
time) are both 10 ns min. The SCC timing parameters
ThA(WR) {Address to /WR High Hold}, ThCE(WR) {/CE to
/WR High Hold} and TdWR(W) {Write data to /WR High
hold} are a minimum of 0 ns. The rising edge of /WR is
early to guarantee these parameter requirements.
This circuit depicts logic for the I/O interface and the
Interrupt Acknowledge Interface for 10 MHz clock of
operation. Figure 13 is the I/O read/write timing chart
(discussions of timing considerations on the Interrupt
Acknowledge cycle and the circuit using EPLD occur
later).
The Z180™ Interfaced with the SCC at MHZ
245 min
160 min
185 min
210 min
241 min
184 min
30 min
30 min
15 min
Value
Value
Application Note
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
6-39
7
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