Z85C3008VSG Zilog, Z85C3008VSG Datasheet - Page 20

• Manufacturer Part Number: Z85C3008VSG
• Description: IC 8MHZ Z8500 CMOS SCC 44-PLCC
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3008VSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Cpu Speed: 8MHz
• Digital Ic Case Style: LCC
• No. Of Pins: 44
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3932; Z85C3008VSG

UM010901-0601
2.1 INTRODUCTION
This chapter covers the system interface requirements
with the SCC. Timing requirements for both devices are
described in a general sense here, and the user should re-
fer to the SCC Product Specification for detailed AC/DC
parametric requirements.
The ESCC and the 85C30 have an additional register,
Write Register Seven Prime (WR7'). Its features include
2.2 Z80X30 INTERFACE TIMING
The Z-Bus
tions with multiplexed address/data buses similar to the
Z8
Two control signals, /AS and /DS, are used by the Z80X30
to time bus transactions. In addition, four other control sig-
nals (/CS0, CS1, R//W, and /INTACK) are used to control
the type of bus transaction that occurs. A bus transaction
is initiated by /AS; the rising edge latches the register ad-
dress on the Address/Data bus and the state of /INTACK
and /CS0.
In addition to timing bus transactions, /AS is used by the
interrupt section to set the Interrupt Pending (IP) bits.
®
, Z8000
®
®
compatible SCC is suited for system applica-
, and Z280
®
.
U
C
I
the ability to read WR3, WR4, WR5, WR7', and WR10.
Both the ESCC and the 85C30 have the ability to deassert
the /DTR//REG pin quickly to ease DMA interface design.
Additionally, the Z85230 features a relaxed requirement for
a valid data bus when the /WR pin goes Low. The effects
of the deeper data FIFOs should be considered when writ-
ing the interrupt service routines. The user should read the
sections which follow for details on these features.
Because of this, /AS must be kept cycling for the inter-
rupt section to function properly.
The Z80X30 generates internal control signals in response
to a register access. Since /AS and /DS have no phase re-
lationship with PCLK, the circuit generating these internal
control signals provides time for metastable conditions to
disappear. This results in a recovery time related to PCLK.
This recovery time applies only to transactions involving
the Z80X30, and any intervening transactions are ignored.
This recovery time is four PCLK cycles, measured from the
falling edge of /DS of one access to the SCC, to the falling
edge of /DS for a subsequent access.
NTERFACING THE
SER
HAPTER
’
S
M
ANUAL
2
SCC/ESCC
2-1
2