Z85C3008VSG Zilog, Z85C3008VSG Datasheet - Page 86
Z85C3008VSG
Manufacturer Part Number
Z85C3008VSG
Description
IC 8MHZ Z8500 CMOS SCC 44-PLCC
Manufacturer
Zilog
Series
SCCr
Specifications of Z85C3008VSG
Processor Type
Z80
Features
Error Detection and Multiprotocol Support
Speed
8MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
44-LCC (J-Lead)
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Cpu Speed
8MHz
Digital Ic Case Style
LCC
No. Of Pins
44
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
85
Rohs Compliant
Yes
Clock Frequency
8MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3932
Z85C3008VSG
Z85C3008VSG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z85C3008VSG
Manufacturer:
Zilog
Quantity:
800
Company:
Part Number:
Z85C3008VSG
Manufacturer:
MAX
Quantity:
74
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UM010901-0601
The arrangement of the sync character in WR6 and WR7
is shown in Figure 4-5.
For those applications requiring any other sync character
length, the SCC makes provision for an external circuit to
Sync Length
6 bits
8 bits
12 bits
16 bits
Table 4-6. Sync Character Length Selection
/SYNC
/RTxC
RxD
WR4,D5
0
0
0
0
SYNC Last-1
Sync7
Sync1
Sync7
Sync3
ADR7
ADR7
Sync7
Sync5
Sync15
Sync11
0
WR4,D4
Sync6
Sync0
Sync6
Sync2
ADR6
ADR6
Sync6
Sync4
Sync14
Sync10
0
0
1
1
1
Figure 4-5. Sync Character Programming
Write Register 6
Sync5
Sync5
Sync5
Sync1
ADR5
ADR5
D7
Write Register 7
Sync5
Sync3
Sync13
Sync9
D7
1
D6
SYNC Last
Figure 4-6. /SYNC as an Input
D6
WR10,D0
D5 D4 D3 D2 D1 D0
Sync4
Sync4
Sync4
Sync0
ADR4
ADR4
D5 D4 D3 D2 D1 D0
Sync4
Sync2
Sync12
Sync8
1
1
0
1
0
Sync3
Sync3
Sync3
ADR3
Sync3
Sync1
Sync11
Sync7
x
1
1
Sync2
Sync2
Sync2
ADR2
Sync2
Sync0
Sync10
Sync6
1
x
1
Data 0
provide a character synchronization signal on the /SYNC
pin. This mode is selected by setting bits D5 and D4 of
WR4 to 1. In this mode, the Sync/Hunt bit in RR0 reports
the state of the /SYNC pin, but the receiver is still placed in
Hunt mode when the external logic is searching for a sync
character match. Two receive clock cycles after the last bit
of the sync character is received, the receiver is in Hunt
mode and the /SYNC pin is driven Low, then character as-
sembly begins on the rising edge of the receive clock. This
immediately precedes the activation of /SYNC (Figure 4-
6). The receiver leaves Hunt mode when /SYNC is driven
Low.
Sync1
Sync1
Sync1
ADR1
Sync1
Sync9
Sync5
1
x
x
1
ADR0
Sync0
Sync0
Sync0
Sync0
Sync8
Sync4
1
x
x
0
Monosync, 8 Bits
Monosync, 6 Bits
Bisync, 16 Bits
Bisync, 12 Bits
SDLC
SDLC (Address Range)
Monosync, 8 Bits
Monosync, 6 Bits
Bisync, 16 Bits
Bisync, 12 Bits
SDLC
Data 1
SCC™/ESCC™ User’s Manual
Data Communication Modes
Data 2
4-11
4
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