Z8S18033VSG Zilog, Z8S18033VSG Datasheet - Page 103

• Manufacturer Part Number: Z8S18033VSG
• Description: IC 33MHZ STATIC Z180 68-PLCC
• Manufacturer: Zilog
• Series: Z8018xr

Specifications of Z8S18033VSG

• Processor Type: Z180
• Features: Enhanced Z180
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Core Size: 8bit
• Cpu Speed: 33MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Rohs Compliant: Yes
• Processor Series: Z8S180X
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 33 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z8S18000ZEM
• Minimum Operating Temperature: 0 C
• Base Number: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4307; Q2431383; Z8S18033VSG

88
Refresh Control Register (RCR: 36H)
UM005003-0703
Bit
Bit/Field
R/W
Reset
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position Bit/Field R/W
7
6
1
–
Z8018x
Family MPU User Manual
0
REFE
REFW
CYC1
REFE
R/W
7
–
Refresh Control Register (RCR)
The RCR specifies the interval and length of refresh cycles, while
enabling or disabling the refresh function.
1
0 R/W
R/W
R/W
REFW
R/W
6
1
Value
0
1
0
1
5
Description
REFE: Refresh Enable
Disables the refresh controller
Enables refresh cycle insertion.
Refresh Wait (bit 6)
Causes the refresh cycle to be two clocks in duration.
Causes the refresh cycle to be three clocks in duration by
adding a refresh wait cycle (TRW).
Cycle Interval — CYC1 and CYC0 specify the interval
(in clock cycles) between refresh cycles. In the case of
dynamic RAMs requiring 128 refresh cycles every 2 ms
(or 256 cycles in every 4 ms), the required refresh interval
is less than or equal to 15.625 ms. Thus, the underlined
values indicate the best refresh interval depending on
CPU clock frequency. CYC0 and CYC1 are cleared to 0
during RESET. Refer to Table 11.
4
?
?
?
3
2
CYC1
R/W
1
0
CYC0
R/W
0
0