Z8S18033VSG Zilog, Z8S18033VSG Datasheet - Page 47
![IC 33MHZ STATIC Z180 68-PLCC](/photos/6/71/67199/269-68-plcc_sml.jpg)
Z8S18033VSG
Manufacturer Part Number
Z8S18033VSG
Description
IC 33MHZ STATIC Z180 68-PLCC
Manufacturer
Zilog
Series
Z8018xr
Specifications of Z8S18033VSG
Processor Type
Z180
Features
Enhanced Z180
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
68-LCC (J-Lead)
Core Size
8bit
Cpu Speed
33MHz
Digital Ic Case Style
PLCC
No. Of Pins
68
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Rohs Compliant
Yes
Processor Series
Z8S180X
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
33 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 3.3 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z8S18000ZEM
Minimum Operating Temperature
0 C
Base Number
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4307
Q2431383
Z8S18033VSG
Q2431383
Z8S18033VSG
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8S18033VSG
Manufacturer:
Zilog
Quantity:
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Company:
Part Number:
Z8S18033VSG
Manufacturer:
ZILOG
Quantity:
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32
UM005003-0703
Z8018x
Family MPU User Manual
•
•
Essentially, the Z80180 operates normally in HALT mode, except that
instruction execution is stopped.
HALT mode can be exited in the following two ways:
•
•
If the interrupt source is masked (individually by enable bit, or globally
by IEF1 state), the Z80180 remains in HALT mode. However, NMI
interrupt initiates the normal NMI interrupt response sequence
independent of the state of IEF1.
HALT timing is illustrated in Figure 20.
The HALT output pin is asserted Low
The external bus activity consists of repeated dummy fetches of the
Op Code following the HALT instruction.
RESET Exit from HALT Mode
If the RESET input is asserted Low for at least six clock cycles,
HALT mode is exited and the normal RESET sequence (restart at
address
Interrupt Exit from HALT mode
When an internal or external interrupt is generated, HALT mode is
exited and the normal interrupt response sequence is initiated.
00000H
) is initiated.
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