Z8S18033VSG Zilog, Z8S18033VSG Datasheet - Page 86

• Manufacturer Part Number: Z8S18033VSG
• Description: IC 33MHZ STATIC Z180 68-PLCC
• Manufacturer: Zilog
• Series: Z8018xr

Specifications of Z8S18033VSG

• Processor Type: Z180
• Features: Enhanced Z180
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Core Size: 8bit
• Cpu Speed: 33MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Rohs Compliant: Yes
• Processor Series: Z8S180X
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 33 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z8S18000ZEM
• Minimum Operating Temperature: 0 C
• Base Number: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4307; Q2431383; Z8S18033VSG

A0
D0
MREQ
–
–
A19
WR
Phi
RD
D7
MI
stacked PC-1. If UFO is
equal to the stacked PC-2.
Bus Release cycle, Refresh cycle, DMA cycle, and WAIT cycle cannot be
inserted just after TTP state which is inserted for TRAP interrupt
sequence. Figure depicts TRAP Timing - 2nd Op Code undefined and
Figure illustrates Trap Timing - 3rd Op Code undefined.
Figure 32.
T1
2nd Op Code
Fetch Cycle
T2
Undefined
Op Code
T3
TRAP Timing Diagram -2nd Op Code Undefined
PC
Ti
Ti
Ti
1
, the starting address of the invalid instruction is
Ti
Ti
T1
T2
SP-1
PCH
PC Stacking
T3
Family MPU User Manual
T1
T2
SP-2
PCL
T3
Restart from 0000H
UM005003-0703
T1
Op Code
Fetch Cycle
T2
0000H
Z8018x
T3
71