Z8S18033VSG Zilog, Z8S18033VSG Datasheet - Page 29

• Manufacturer Part Number: Z8S18033VSG
• Description: IC 33MHZ STATIC Z180 68-PLCC
• Manufacturer: Zilog
• Series: Z8018xr

Specifications of Z8S18033VSG

• Processor Type: Z180
• Features: Enhanced Z180
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Core Size: 8bit
• Cpu Speed: 33MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Rohs Compliant: Yes
• Processor Series: Z8S180X
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 33 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z8S18000ZEM
• Minimum Operating Temperature: 0 C
• Base Number: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4307; Q2431383; Z8S18033VSG

14
UM005003-0703
Z8018x
Family MPU User Manual
Central Processing Unit
The CPU is microcoded to provide a core that is object code compatible
with the Z80 CPU. It also provides a superset of the Z80 instruction set,
including 8-bit multiply and divide. This core has been enhanced to allow
many of the instructions to execute in fewer clock cycles.
DMA Controller
The DMA controller provides high speed transfers between memory and
I/O devices. Transfer operations supported are memory-to-memory,
memory to/from I/O and I/O to I/O. Transfer modes supported are
REQUEST, BURST, and CYCLE STEAL. DMA transfers can access the
full 1MB addressing range with a block length up to 64KB, and can cross
over 64K boundaries.
Asynchronous Serial Communications Interface (ASCI)
The ASCI logic provides two individual full-duplex UARTs. Each
channel includes a programmable baud rate generator and modem control
signals. The ASCI channels can also support a multiprocessor
communications format.
Programmable Reload Timer (PRT)
This logic consists of two separate channels, each containing a 16-bit
counter (timer) and count reload register. The time base for the counters is
derived from the system clock (divided by 20) before reaching the
counter. PRT channel 1 provides an optional output to allow for
waveform generation.
Clocked Serial I/O (CSIO)
The CSIO channel provides a half-duplex serial transmitter and receiver.
This channel can be used for simple high-speed data connection to
another microprocessor or microcomputer.