Z8S18033VSG Zilog, Z8S18033VSG Datasheet - Page 99
![IC 33MHZ STATIC Z180 68-PLCC](/photos/6/71/67199/269-68-plcc_sml.jpg)
Z8S18033VSG
Manufacturer Part Number
Z8S18033VSG
Description
IC 33MHZ STATIC Z180 68-PLCC
Manufacturer
Zilog
Series
Z8018xr
Specifications of Z8S18033VSG
Processor Type
Z180
Features
Enhanced Z180
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
68-LCC (J-Lead)
Core Size
8bit
Cpu Speed
33MHz
Digital Ic Case Style
PLCC
No. Of Pins
68
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Rohs Compliant
Yes
Processor Series
Z8S180X
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
33 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 3.3 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z8S18000ZEM
Minimum Operating Temperature
0 C
Base Number
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4307
Q2431383
Z8S18033VSG
Q2431383
Z8S18033VSG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8S18033VSG
Manufacturer:
Zilog
Quantity:
40
Company:
Part Number:
Z8S18033VSG
Manufacturer:
ZILOG
Quantity:
6 252
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84
UM005003-0703
Z8018x
Family MPU User Manual
Note: RETI machine cycles 9 and 10 not shown.
A0
M1 (M1E = 1)
M1 (M1E = 0)
–
A18 (A19)
Return from Subroutine (RETI) Instruction Sequence
When the
the RETI instruction sequence. The Z8X180 then refetches the RETI
instruction with four T-states in the
peripherals time to decode that cycle (See Figure 42). This procedure
allows the internal interrupt structure of the peripheral to properly decode
the instruction and behave accordingly.
The M1E bit of the Operation Mode Control Register (OMCR) must be
set to
instruction sequence. This condition is the desired operation when Z80
peripherals are connected to the Z8018X.
Figure 42.
The RETI instruction takes 22 T-states and 10 machine cycles. Table 10
lists the conditions of all the control signals during this sequence for the
D0
MREQ
–
Phi
RD
D7
ST
0
so that M1 signal is active only during the refetch of the RETI
T1
EDH
RETI Instruction Sequence
T2
/
4DH
PC
EDH
T3 T1
sequence is fetched by the Z8X180, it is recognized as
T2
4DH
T3
PC + 1
Ti
EDH
Ti
cycle allowing the Z80
Ti
T1
T2
EDH
PC
T3
Ti
T1
T2
PC + 1
4DH
T3
T1
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