EZ80190AZ050SG Zilog, EZ80190AZ050SG Datasheet - Page 108

• Manufacturer Part Number: EZ80190AZ050SG
• Description: IC WEBSERVER 8 BIT 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80190x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3866; EZ80190AZ050SG

Table 43. I
PS006614-1208
Code
18h
20h
38h
68h
78h
B0h
Note: W = Write bit. The lsb is cleared to 0.
Addr+W transmitted,
Addr+W transmitted,
Arbitration lost
Arbitration lost, SLA+W
Arbitration lost,
Arbitration lost, SLA+R
I
ACK received
ACK not received
received, ACK
transmitted
General call addr
received, ACK
transmitted
received, ACK
transmitted
2
C State
2
C Master Transmit Status Codes
If 10-bit addressing is being used, then the status code is
a 10-bit address, plus the write bit, are successfully transmitted.
After this interrupt is serviced and the second part of the 10-bit address is transmitted, the
I2Cx_SR register contains one of the codes in
Microprocessor Response
For a 7-bit address: Write a
byte to DATA, clear IFLG
Or set STA, clear IFLG
Or set STP, clear IFLG
Or set STA & STP, clear IFLG
For a 10-bit address: Write an
extended address byte to
DATA, clear IFLG
Same as code 18h
Clear IFLG
Or set STA, clear IFLG
Clear IFLG, ACK = 0
Or clear IFLG, ACK = 1
Same as code 68h
Write byte to DATA, clear IFLG,
clear ACK = 0
Or write byte to DATA, clear
IFLG, set ACK = 1
Table 44
Next I
Transmit data byte,
receive ACK
Transmit repeated
START
Transmit STOP
Transmit STOP then
START
Transmit extended
address byte
Same as code 18h
Return to the IDLE state
Transmit START when
bus is free
Receive data byte,
transmit NACK
Receive data byte,
transmit ACK
Same as code 68h
Transmit last byte, receive
ACK
Transmit data byte,
receive ACK
2
on page 99.
C Action
18h
or
Product Specification
20h
after the first part of
I2C Serial I/O Interface
98