EZ80190AZ050SG Zilog, EZ80190AZ050SG Datasheet - Page 36
![IC WEBSERVER 8 BIT 50MHZ 100LQFP](/photos/6/76/67664/269-100-lqfp_sml.jpg)
EZ80190AZ050SG
Manufacturer Part Number
EZ80190AZ050SG
Description
IC WEBSERVER 8 BIT 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80190AZ050SG.pdf
(221 pages)
Specifications of EZ80190AZ050SG
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80190x
Core
eZ80
Data Bus Width
8 bit
Program Memory Type
ROMLess
Data Ram Size
8 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3866
EZ80190AZ050SG
EZ80190AZ050SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EZ80190AZ050SG
Manufacturer:
ZiLOG
Quantity:
135
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Table 2. Register Map (Continued)
PS006614-1208
Address
(hex)
Universal Zilog Interface Blocks
B6
B7
B8
B8
B9
BA
BB
BC
BC
BD
BE
BF
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
Mnemonic
SPI0_CTL
SPI0_SR
SPI0_RBR
SPI0_TSR
Not Accessible
SPI1_CTL
SPI1_SR
SPI1_RBR
SPI1_TSR
Not Accessible
Not Accessible
Not Accessible
UART0_RBR
UART0_THR
BRG0_DLR_L
BRG0_DLR_H
UART0_IER
UART0_IIR
UART0_FCTL
UART0_LCTL
UART0_MCTL
UART0_LSR
UART0_MSR
UART0_SPR
I2C0_SAR
I2C0_xSAR
Name
SPI 0 Control Register
SPI 0 Status Register
SPI 0 Receive Buffer Register
SPI 0 Transmit Shift Register
SPI 1 Control Register
SPI 1 Status Register
SPI1 Receive Buffer Register
SPI1 Transmit Shift Register
UART 0 Receive Buffer Register
UART 0 Transmit Holding Register
BRG 0 Divisor Latch Register—Low Byte
BRG 0 Divisor Latch Register—High Byte
UART 0 Interrupt Enable Register
UART 0 FIFO Control Register
UART 0 Line Control Register
UART 0 Line Status Register
UART 0 Modem Status Register
UART 0 Scratch Pad Register
I
I
UART 0 Interrupt Identification Register
UART 0 Modem Control Register
2
2
C 0 Slave Address Register
C 0 Extended Slave Address Register
Reset
(hex)
XX
XX
XX
XX
XX
XX
02
00
60
X0
04
00
04
00
00
01
00
00
00
00
00
00
Product Specification
Access
CPU
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
W
W
R
R
R
R
R
R
R
R
Register Map
eZ80190
Page
106
108
109
108
106
108
109
108
101
102
104
105
128
128
No.
89
86
65
65
90
91
98
99
26
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