EZ80190AZ050SG Zilog, EZ80190AZ050SG Datasheet - Page 168

• Manufacturer Part Number: EZ80190AZ050SG
• Description: IC WEBSERVER 8 BIT 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80190x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3866; EZ80190AZ050SG

PS006614-1208
Bit
Position
4
BRK_ADDR0
2
IGN_LOW_1
1
IGN_LOW_0
0
SINGLE_STEP
Value Description
0
1
0
1
0
1
0
1
The ZDI break, upon matching break address 0, is disabled.
The ZDI break, upon matching break address 0, is enabled.
ZDI asserts a break when the CPU address, ADDR[23:0],
matches the value in the ZDI Address Match 1 registers,
{ZDI_ADDR0_U, ZDI_ADDR0_H, ZDI_ADDR0_L}. If the
IGN_LOW_0 bit is set to 1, ZDI asserts a break with the upper
two bytes of the CPU address, ADDR[23:8], and matches the
value in the ZDI Address Match 0 High and Low Byte registers,
{ZDI_ADDR0_U, ZDI_ADDR0_LH}. The lower byte of the
address is ignored. Breaks can only occur on an instruction
boundary. If the address is not the beginning of an instruction,
then the break occurs at the end of the current instruction.The
break is implemented by setting the BRK_NEXT bit to 1. The
BRK_NEXT bit must be reset to 0 to release the break.
The Ignore the Low byte function of the ZDI Address Match 1
registers is disabled. If BRK_ADDR1 is set to 1, ZDI initiates a
break when the entire 24-bit address, ADDR[23:0], matches
the 3-byte value {ZDI_ADDR1_U, ZDI_ADDR1_H,
ZDI_ADDR1_L}.
The Ignore the Low byte function of the ZDI Address Match 1
registers is enabled. If BRK_ADDR1 is set to 1, ZDI initiates a
break when only the upper 2 bytes of the 24-bit address,
ADDR[23:8], match the 2-byte value {ZDI_ADDR1_U,
ZDI_ADDR1_H}. As a result, a break can occur anywhere
within a 256-byte page.
The Ignore the Low byte function of the ZDI Address Match 1
registers is disabled. If BRK_ADDR0 is set to 1, ZDI initiates a
break when the entire 24-bit address, ADDR[23:0], matches
the 3-byte value {ZDI_ADDR0_U, ZDI_ADDR0_H,
ZDI_ADDR0_L}.
The Ignore the Low byte function of the ZDI Address Match 1
registers is enabled. If the BRK_ADDR1 is set to 0, ZDI
initiates a break when only the upper 2 bytes of the 24-bit
address, ADDR[23:8], match the 2 bytes value
{ZDI_ADDR0_U, ZDI_ADDR0_H}. As a result, a break can
occur anywhere within a 256-byte page.
ZDI SINGLE STEP mode is disabled.
ZDI SINGLE STEP mode is enabled. ZDI asserts a break
following execution of each instruction.
Product Specification
Zilog Debug Interface
eZ80190
158