A80386DX16 Intel, A80386DX16 Datasheet - Page 14

• Manufacturer Part Number: A80386DX16
• Description: IC MPU 32-BIT 5V 16MHZ 132-PGA
• Manufacturer: Intel

Specifications of A80386DX16

• Processor Type: 386DX
• Features: 32-bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-PGA
• Family Name: Intel386 DX
• Device Core Size: 32b
• Frequency (max): 16MHz
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 132
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 807050

Intel386
LDTR and TR
These registers hold the 16-bit selector for the LDT
descriptor and the TSS descriptor respectively
The LDT and TSS segments since they are task-
specific segments are defined by selector values
stored in the system segment registers Note that a
segment descriptor register (programmer-invisible)
is associated with each system segment register
2 3 8 Debug and Test Registers
Debug Registers The six programmer accessible
debug registers provide on-chip support for debug-
ging Debug Registers DR0– 3 specify the four linear
breakpoints The Debug Control Register DR7 is
used to set the breakpoints and the Debug Status
Register DR6 displays the current state of the
breakpoints The use of the debug registers is de-
scribed in section 2 12 Debugging support
14
LDTR
GDTR
DEBUG REGISTERS
31
LINEAR BREAKPOINT ADDRESS 0
LINEAR BREAKPOINT ADDRESS 1
LINEAR BREAKPOINT ADDRESS 2
LINEAR BREAKPOINT ADDRESS 3
Int e l reserved Do not define
Int e l reserved Do not define
BREAKPOINT STATUS
BREAKPOINT CONTROL
TEST REGISTERS (FOR PAGE CACHE)
31
TEST CONTROL
TEST STATUS
IDTR
TR
Figure 2-8 Debug and Test Registers
SYSTEM SEGMENT
47 32-BIT LINEAR BASE ADDRESS 16 15
15
TM
REGISTERS
SELECTOR
SELECTOR
DX MICROPROCESSOR
SYSTEM ADDRESS REGISTERS
Figure 2-7 System Address and System Segment Registers
0
32-BIT LINEAR BASE ADDRESS
0
0
DESCRIPTOR REGISTERS (AUTOMATICALLY LOADED)
DR0
DR1
DR2
DR3
DR4
DR5
DR6
DR7
TR6
TR7
LIMIT
Test Registers Two registers are used to control
the testing of the RAM CAM (Content Addressable
Memories) in the Translation Lookaside Buffer por-
tion of the Intel386 DX TR6 is the command test
register and TR7 is the data register which contains
the data of the Translation Lookaside buffer test
Their use is discussed in section 2 11 Testability
Figure 2-8 shows the Debug and Test registers
2 3 9 Register Accessibility
There are a few differences regarding the accessibil-
ity of the registers in Real and Protected Mode Ta-
ble 2-1 summarizes these differences See Section
4 Protected Mode Architecture for further details
2 3 10 Compatibility
In the preceding register descriptions note cer-
tain Intel386 DX register bits are Intel reserved
When reserved bits are called out treat them as
fully undefined This is essential for your soft-
ware compatibility with future processors Fol-
low the guidelines below
1) Do not depend on the states of any unde-
2) Do not depend on the states of any unde-
3) Do not depend on the ability to retain infor-
4) When loading registers always load the unde-
COMPATIBILITY WITH FUTURE PROCESSORS
0
fined bits when testing the values of defined
register bits Mask them out when testing
fined bits when storing them to memory or
another register
mation written into any undefined bits
fined bits as zeros
VERY IMPORTANT NOTE
32-BIT SEGMENT LIMIT
ATTRIBUTES