MPC8379EVRAJF Freescale Semiconductor, MPC8379EVRAJF Datasheet - Page 14

• Manufacturer Part Number: MPC8379EVRAJF
• Description: MPU PWRQUICC II 533MHZ 689TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8379EVRAJF

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 533MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 689-TePBGA II
• Maximum Clock Frequency: 533 MHz
• Operating Supply Voltage: 1.8 V to 2.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 533MHz
• Embedded Interface Type: DUART, HSSI, I2C, IPIC, JTAG, SPI, USB
• Digital Ic Case Style: BGA
• No. Of Pins: 689
• Rohs Compliant: Yes
• For Use With: MPC8377E-RDBA - BOARD REF DES MPC8377 REV 2.1MPC8377E-MDS-PB - BOARD MODULAR DEV SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Clock Input Timing
4.2
The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on
whether the device is configured in PCI host or PCI agent mode.
(CLKIN/PCI_CLK) AC timing specifications for the device.
4.3
Table 9
14
At recommended operating conditions with LV
CLKIN/PCI_CLK frequency
CLKIN/PCI_CLK cycle time
CLKIN/PCI_CLK rise and fall time
CLKIN/PCI_CLK duty cycle
CLKIN/PCI_CLK jitter
Notes:
1
2
3
4
5
6
EC_GTX_CLK125 frequency
EC_GTX_CLK125 cycle time
EC_GTX_CLK rise and fall time
EC_GTX_CLK125 duty cycle
EC_GTX_CLK125 jitter
Notes:
1
2
Caution: The system, core and security block must not exceed their respective maximum or minimum operating frequencies.
Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 V and 2.7 V.
Timing is guaranteed by design and characterization.
This represents the total input jitter-short term and long term-and is guaranteed by design.
The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low to
allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.
Spread spectrum is allowed up to 1% down-spread on CLKIN/PCI_CLK up to 60 KHz.
Rise and fall times for EC_GTX_CLK125 are measured from 0.5 and 2.0 V for LV
LV
EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. The EC_GTX_CLK125
duty cycle can be loosened from 47%/53% as long as the PHY device can tolerate the duty cycle generated by the eTSEC
GTX_CLK. See
reference clock.
DD
= 3.3 V.
provides the eTSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications.
Parameter/Condition
AC Electrical Characteristics
eTSEC Gigabit Reference Clock Timing
1000Base-T for RGMII, RTBI
Parameter
Section 8.2.2, “RGMII and RTBI AC Timing
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
LV
LV
Table 9. EC_GTX_CLK125 AC Timing Specifications
DD
DD
= 2.5 V
= 3.3 V
Table 8. CLKIN AC Timing Specifications
DD
= 2.5 ± 0.125 mV/ 3.3 V ± 165 mV
t
G125R
t
G125H
Symbol
t
KHK
Symbol
t
t
t
G125
G125
f
t
KH
—
CLKIN
CLKIN
/t
/t
/t
—
G125F
, t
G125
CLKIN
KL
Specifications,”
Min
47
—
—
—
—
Min
0.6
25
15
40
—
Table 8
for the duty cycle for 10Base-T and 100Base-T
Typical
Typical
1.0
125
—
—
—
—
—
—
—
8
DD
= 2.5 V and from 0.6 and 2.7 V for
provides the clock input
66.666
± 150
Max
2.3
40
60
±150
Max
0.75
1.0
53
—
—
Freescale Semiconductor
MHz
Unit
ns
ns
ps
%
MHz
Unit
ns
ns
ps
%
Notes
Notes
1, 6
4, 5
—
2
3
—
—
1
2
2