GCIXP1200GC Intel, GCIXP1200GC Datasheet - Page 14

• Manufacturer Part Number: GCIXP1200GC
• Description: IC MPU NETWORK 232MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1200GC

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 232MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 839429

Intel
Errata
7.
Problem:
Implication:
Workaround:
Status:
8.
Problem:
Implication:
Workaround:
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9.
Problem:
Implication:
Workaround:
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14
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IXP1200 Network Processor
SDRAM Memory Reference with SDRAM optimize_ mem Instruction
Qualifier
Due to an arbitration issue, when the SDRAM optimize_mem instruction qualifier is used, it is
possible that an SDRAM reference may not be serviced in a timely manner. This can occur if ALL
memory references are to the same bank, AND some references are qualified with optimize_mem,
AND the non-optimize_mem references consistently keep the Order Queue non-empty.
The Order Queue will be continuously serviced, thus causing the same-bank Queue to be unfairly
arbitrated.
Workaround A
Workaround B
Fixed
SRAM Memory Reference with SRAM optimize_ mem Instruction Qualifier
Due to an arbitration issue, when the SRAM optimize_mem instruction qualifier is used, if
frequent references are issued to the Order Queue, then the Read Queue may be stalled for service.
Also possible, but less problematic, the Priority Queue can also cause stalling of references to the
Order Queues.
Results in unexpectedly long latencies in Read Queue references. It is assumed that microcode
carefully manages references to the priority queue so the possibility of this occurring would be
remote.
Careful use of optimize_mem. The queue priority is:
While this allows the use of optimize_mem to improve performance, it is possible for references
issued to the Read Queue to starve references issued to the Order Queue. The microcoder should
exercise careful use of the optimize_mem qualifier.
Fixed
Clock Synchronization Differences Between StrongARM* Core and IX Bus
Clock
Due to clock synchronization differences between the StrongARM* core and the IX Bus clock, it is
possible that the IX Bus XMIT_PTR register may be incremented incorrectly during IX BUS data
transfers.
Transmit operations may stop.
None known.
Fixed
Issue references to the opposite queue regularly. For example, if a reference is
issued to the Even Queue, try to schedule a successive reference to the Odd Queue.
This forces the arbiter to service the Even Queue.
Avoid the use of the optimize_mem qualifier.
1) Priority Queue
2) Read Queue, if last SRAM reference was a read
3) Order Queue
4) Read Queue
Specification Update