GCIXP1200GC Intel, GCIXP1200GC Datasheet - Page 23

• Manufacturer Part Number: GCIXP1200GC
• Description: IC MPU NETWORK 232MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1200GC

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 232MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 839429

Status:
33.
Problem:
Implication:
Workaround:
Status:
34.
Problem:
Implication:
Workaround:
Status:
Specification Update
got_it#:
Fixed
Read-Lock CAM Operations from the StrongARM* Core to SRAM
StrongARM* core instructions that use the SRAM CAM address range (0x1200 0000 - 0x127F
FFFF) to perform a read-locked access can not rely on the lock attempt succeeding.
StrongARM* applications that share data structures with the Microengines cannot rely on the
SRAM CAM to provide atomic access to those data structures. When a StrongARM* application
issues a read_lock operation, the operation may be placed in the read_lock fail queue by the SRAM
controller. The application determines whether or not the operation was placed in the read_lock fail
queue by checking the value of the RLS bit of the SRAM_CSR register. To determine when a
failed read_lock request is eventually moved from the read_lock rail queue to the CAM, the
application polls the SRAM_CSR register until the RLRS bit is set to 1. The SRAM controller is
incorrectly failing to set the RLRS bit when read_lock operation is moved from the read_lock fail
queue to the SRAM CAM. Therefore, a StrongARM* application is not notified when a read_lock
request is ultimately granted. This will cause locks to be placed in the CAM without application
awareness.
None. If a mutual exclusion mechanism is required, the following approaches may be used in place
of the SRAM CAM:
NoFix
IXP1200 PCI_INT_LAT Register Bits [11:8]
Bits [11:8] of the IXP1200 PCI_INT_LAT register are writable from PCI. These bits correspond to
PCI Interrupt Configuration Register bits [11:8]. These bits should be read-only from PCI.
The IXP1200 interrupt to PCI (INTA#) could be inadvertently disabled by BIOS or PCI
plug-and-play drivers if these bits are written by PCI enumeration code to a value of 0000.
The StrongARM* core can poll this register and rewrite correct value after BIOS or a driver writes
this register.
Fixed
1. Use the SRAM Bit Test & Set and Bit Test & Clear atomic operations (refer to Errata 32).
2. Create a Microengine service thread that will access the SRAM CAM on behalf of the
; got test-and-set
;
; Place code here to access locked resource
;
; release test-and-set
immed[$xfer, TANDSBIT]
sram[bit_wr, $xfer, addr, 0, clear_bits], ctx_swap
br[start#]
StrongARM* application. For information on building a service thread that is callable from the
StrongARM* core refer to the description of the SHRIMP API and Dispatch Library in the
IXP1200 Network Processor Family Microcode Software Reference Manual.
Intel
®
IXP1200 Network Processor
Errata
23