GCIXP1200GC Intel, GCIXP1200GC Datasheet - Page 30

• Manufacturer Part Number: GCIXP1200GC
• Description: IC MPU NETWORK 232MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1200GC

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 232MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 839429

Intel
Errata
Workaround:
30
®
IXP1200 Network Processor
Note: Great care must be taken to ensure that different optional tokens are carried over to the workaround
Two workarounds have been developed and are described below:
Workaround 1 requires two Microengine Instruction Control Store locations, but results in one
extra SRAM bus write cycle. It is possible to eliminate the extra bus cycle by suitably modifying
the transfer register, address, and, ref_cnt fields, but may result extra Microengine instructions
needed to compute the address. A simple case is illustrated in the examples below for this.
Workaround 2 does not have the extra bus access but may require a third ctx_arb[SRAM]
instruction if the program needs to wait for completion of the command. Examples shown below
will illustrate this point.
to ensure correct program flow. The examples below are given to illustrate some key
considerations.
Example A – No optional tokens.
Original code
SRAM[WRITE_UNLOCK, $x1, sAddr, 0, 3]
Workaround 1
SRAM[WRITE, $x2, sAddr, 1, 2]
SRAM[WRITE_UNLOCK, $x1, sAddr, 0, 1]
Workaround 2
SRAM[WRITE, $x1, sAddr, 0, 3]
SRAM[UNLOCK, --, sAddr, 0, 1]
Example B – CTX_SWAP optional token.
Original code
SRAM[WRITE_UNLOCK, $x1, sAddr, 0, 3], ctx_swap
Workaround 1
SRAM[WRITE, $x2, sAddr,1, 2]
SRAM[WRITE_UNLOCK, $x1, sAddr, 0, 1],ctx_swap
Workaround 2
SRAM[WRITE, $x1, sAddr, 0, 3], sig_done
SRAM[UNLOCK, --, sAddr, 0, 1]
CTX_ARB[SRAM]
Example C - When the priority queue is used, both requests must use the
same queue.
Original code
SRAM[WRITE_UNLOCK, $x1, sAddr, 0, 3], priority, ctx_swap
Workaround 1
SRAM[WRITE, $x2, sAddr, 1, 2], priority
SRAM[WRITE_UNLOCK, $x1, sAddr, 0, 1], priority, ctx_swap
1. Break the SRAM[WRITE_UNLOCK,..., ref_cnt] instruction into a SRAM[write, …, ref_cnt]
2. Break the SRAM[WRITE_UNLOCK,....], instruction into a SRAM[write, …, ref_cnt] and
and SRAM[WRITE_UNLOCK,..., 1] pair.
SRAM[UNLOCK,..., 1] pair.
Specification Update