IDT79RC32T351-133DH IDT, Integrated Device Technology Inc, IDT79RC32T351-133DH Datasheet
IDT79RC32T351-133DH
Specifications of IDT79RC32T351-133DH
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IDT79RC32T351-133DH Summary of contents
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Features List ◆ RC32300 32-bit Microprocessor – Enhanced MIPS-II ISA – Enhanced MIPS-IV cache prefetch instruction – DSP Instructions – MMU with 16-entry TLB – 8kB Instruction cache, 2-way set associative – 2kB Data cache, 2-way set associative – Per ...
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IDT 79RC32351 – Supports burst transfers USB ◆ – Revision 1.1 compliant – USB slave device controller th – Supports a 6 USB endpoint – Full speed operation at 12 Mb/s – Supports control, interrupt, bulk and isochronous endpoints – ...
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IDT 79RC32351 Device Overview The RC32351 is a “System on a Chip” which contains a high perfor- mance 32-bit microprocessor. The microprocessor core is used exten- sively at the heart of the device to implement the most needed functionalities in ...
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IDT 79RC32351 Thermal Considerations The RC32351 consumes less than 1.5 W peak power and is guaran- teed in an ambient temperature range of 0° to +70° C (commercial). Revision History January 7, 2002: Initial publication. May 20, 2002: Added values ...
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IDT 79RC32351 Pin Description Table The following table lists the functions of the pins provided on the RC32351. Some of the functions listed may be multiplexed onto the same pin. To define the active polarity of a signal, a suffix ...
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IDT 79RC32351 Name Type I/O Type RWN O High Drive Read or Write. This signal indicates if the transaction on the memory and peripheral bus is a read transaction or a write transaction. A high level indicates a read from ...
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IDT 79RC32351 Name Type I/O Type GPIOP[5] I/O Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin. with STI Alternate function: UART channel 0 data set ready, U0DSRN. GPIOP[6] I/O Low Drive General ...
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IDT 79RC32351 Name Type I/O Type GPIOP[24] I/O Low Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin. with STI Alternate function: ATM receive PHY address, RXADDR[0]. GPIOP[25] I/O Low Drive General Purpose I/O. ...
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IDT 79RC32351 Name Type I/O Type MIIMDIOP I/O Low Drive MII Management Data. This bidirectional signal is used to transfer data between the station management entity and the with STI ethernet PHY. MIIRXCLKP I STI MII Receive Clock. This clock ...
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IDT 79RC32351 Name Type I/O Type EJTAG_TRST_N I STI EJTAG Test Reset. EJTAG_TRST_N is an active-low signal for asynchronous reset of only the EJTAG/ICE controller. EJTAG_TRST_N requires an external pull-up on the board. EJTAG/ICE enable is selected during reset using ...
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IDT 79RC32351 Name Type I/O Type U0DTRN O Low Drive UART channel 0 data terminal ready. Primary function: General Purpose I/O, GPIOP[4]. At reset, this pin defaults to primary function GPIOP[4] if CPU/DMA Sta- tus Mode enable is not selected ...
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IDT 79RC32351 Signal MDATA[2:0] Clock Multiplier. This field specifies the value by which the system clock (CLKP) is multiplied internally to generate the CPU pipeline clock. 0x0 - multiply by 2 0x1 - multiply by 3 0x2 - multiply by ...
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IDT 79RC32351 Logic Diagram The following Logic Diagram shows the primary pin functions of the RC32351. CLKP SYSCLKP COLDRSTN RSTN USBDP USBDN USBCLKP MIIRXDP[3:0] MIIRXDVP MIIRXERP MIIRXCLKP MIICRSP MIICOLP MIITXDP[3:0] MIITXENP MIITXERP MIITXCLKP MIIMDCP MIIMDIOP JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO VccCore ...
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IDT 79RC32351 Clock Parameters (Ta = 0°C to +70°C Commercial, Vcc I/O = +3.3V±5%, V Parameter 1 Internal CPU pipeline clock 2,3,4 CLKP 1 The CPU pipeline clock speed is selected during cold reset by the boot configuration vector (see ...
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IDT 79RC32351 AC Timing Definitions Below are examples of the AC timing characteristics used throughout this document. clock Output signal 1 Output signal 2 Input Signal 1 Signal Symbol Tperiod Clock period. Tlow Clock low. Amount of time the clock ...
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IDT 79RC32351 AC Timing Characteristics (Ta = 0°C to +70°C Commercial, Vcc I/O = +3.3V±5%,V Signal Symbol Reset and System COLDRSTN Tpw1 Trise1 1 RSTN Tdo2 MDATA[15:0] Thld3 Boot Configuration Vector INSTP Tdo CPUP Tdo DMAP Tdo 2 DMAREQN Tpw ...
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IDT 79RC32351 2 1 CLKP SYSCLKP COLDRSTN Tdo2 RSTN MDATA[31:0] BDIRN BOEN[0] >= 100 ms Tpw1 1. COLDRSTN asserted by external logic. 2. The RC32351 asserts RSTN, asserts BOEN[0] low, drives BDIRN low, and tri-states the data bus in response. ...
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IDT 79RC32351 1 CLKP COLDRSTN RSTN MDATA[31:0] Active Mem Control Signals 1. Warm reset condition caused by either RSTN asserted, write to reset register, or bus transaction timer time-out. The RC32351 asserts RSTN out- put low in response. 2. The ...
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IDT 79RC32351 Signal Symbol Memory and Peripheral Bus - SDRAM Access MDATA[31:0] Tsu1 Thld1 Tdo1 Tdz1 Tzd1 MADDR[20:2], BWEN[3:0] Tdo2 CASN, RASN, SDCSN[1:0], Tdo3 SDWEN CKENP Tdo4 BDIRN Tdo5 BOEN[1:0] Tdo6 SYSCLKP rising Tdo7 SDCLKINP Tperiod8 Thigh8,Tlow8 Trise8,Tfall8 Tdelay8 Table ...
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IDT 79RC32351 Signal Symbol Memory and Peripheral Bus - Device Access MDATA[31:0] Tsu1 Thld1 Tdo1 Tdz1 Tzd1 WAITACKN, BRN Tsu Thld MADDR[21:0] Tdo2 Tdz2 Tzd2 MADDR[25:22] Tdo3 Tdz3 Tzd3 BDIRN, BOEN[0] Tdo4 Tdz4 Tzd4 BGN, BWEN[3:0], OEN, Tdo5 RWN Tdz5 ...
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IDT 79RC32351 CLKP SYSCLKP Tdo2 MADDR[21:0] Tdo2 BWEN[3:0] 1111 Tdo3 CMD[2:0]* NOP READ Tdo3 SDCSN[1:0] 11 Chip-Sel Tdo5 BDIRN Tdo6 11 BOEN[1:0] Tdz1 MDATA[31:0] SDCLKINP * NOTE: CMD[2:0] = {RASN, CASN, SDWEN} Figure 8 Memory and Peripheral Bus AC Timing ...
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IDT 79RC32351 CLKP SYSCLKP MADDR[21:0] BWEN[3:0] 1111 CMD[2:0]* NOP SDCSN[1:0] 11 BDIRN BOEN[1:0] 11 MDATA[31:0] * NOTE: CMD[2:0] = {RASN, CASN, SDWEN} Figure 10 Memory and Peripheral Bus AC Timing Waveform - SDRAM Write Access SDRAM samples Tdo2 write data ...
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IDT 79RC32351 CLKP MADDR[21:0] MADDR[25:22] RWN CSN[3:0] BWEN[3:0] OEN Tdz1 MDATA[31:0] Tdo4 BDIRN BOEN[0] WAITACKN Figure 11 Memory and Peripheral Bus AC Timing Waveform - Device Read Access Tdo2 Addr[21:0] Tdo3 Addr[25:22] Tdo6 1111 Tdo5 RC32351 samples read data Tdo4 ...
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IDT 79RC32351 CLKP MADDR[21:0] MADDR[25:22] RWN CSNx BWEN[3:0] 1111 OEN MDATA[31:0] BDIRN BOEN[0] WAITACKN Figure 12 Memory AC and Peripheral Bus Timing Waveform - Device Write Access Tdo2 Addr[21:0] Tdo3 Addr[25:22] Tdo5 Tdo6 Tdo5 Byte Enables Tdo1 Data Tdo4 24 ...
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IDT 79RC32351 Signal Symbol 1,2 Ethernet MIIRXCLKP, MIITXCLKP Tperiod1 Thigh1,Tlow1 Trise1,Tfall1 MIIRXCLKP, MIITXCLKP Tperiod1 Thigh1,Tlow1 Trise1,Tfall1 MIIRXDP[3:0], MIIRXDVP, Tsu2 MIIRXERP Thld2 MIITXDP[3:0], MIITXENP, Tdo3 MIITXERP MIIMDCP Tperiod4 Thigh4,Tlow4 Trise4 Tfall4 MIIMDIOP Tsu5 Thld5 Tdo5 1 Ethernet clock (MIIRXCLKP and MIITXCLKP) ...
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IDT 79RC32351 MIIRXDVP, MIIRXDP[3:0], MIIRXERP MIITXENP, MIITXDP[3:0], MMTXERP MIIRXCLKP Thld2 Tsu2 MIITXCLKP Tdo3 MIIMDCP Tdo5 MIIMDIOP (output) MIIMDIOP (input) Figure 13 Ethernet AC Timing Waveform Thigh1 Tlow1 Tlow1 Tperiod1 Thigh1 Tlow1 Tlow1 Tperiod1 Tdo3 Tlow4 Tlow4 Thigh4 ...
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IDT 79RC32351 Signal Symbol 1,2 ATM Interface, Utopia Mode 1 RXCLKP, TXCLKP Tperiod1 Thigh1,Tlow1 Trise1,Tfall1 1 RXCLKP, TXCLKP Tperiod1 Thigh1,Tlow1 Trise1,Tfall1 RXCLKP, TXCLKP Tperiod1 Thigh,Tlow1 Trise1,Tfall1 TXFULLN Thld2 TXDATA[7:0], TXSOC, TXENBN, TXADDR[1:0] RXDATA[7:0], RXEMP- TYN, RXSOC Thld4 RXADDR[1:0], RXENBN 1. ...
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IDT 79RC32351 ATM Pin Name ATMINP[0] ATMINP[1] ATMINP[2] ATMINP[3] ATMINP[4] ATMINP[5] ATMINP[6] ATMINP[7] ATMINP[8] ATMINP[9] ATMINP[10] ATMINP[11] ATMIOP[0] ATMIOP[1] ATMOUTP[0] ATMOUTP[1] ATMOUTP[2] ATMOUTP[3] ATMOUTP[4] ATMOUTP[5] ATMOUTP[6] ATMOUTP[7] ATMOUTP[8] ATMOUTP[9] GPIOP[22] GPIOP[23] GPIOP[24] GPIOP[25] Utopia Level 1 Utopia Level 2 RXDATA[0] ...
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IDT 79RC32351 Signal Symbol USB 1 USBCLKP Tperiod1 Thigh1,Tlow1 Trise1,Tfall1 Tjitter1 USBDN, USBDP Trise2 Tfall2 USBDN and USBDP Rise and Fall Time Matching Data valid period Tstate Skew between USBDN and USBDP Source data jitter Receive data jitter Source EOP ...
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IDT 79RC32351 USBCLKP Tjitter1 USBDN 10% USBDP Tfdrate USBDN USBDP Signal Symbol UART U0SINP, U0RIN, U0DCDN, Tsu U0DSRN, U0CTSN, Thld U1SINP, U1DSRN, U1CTSN U0SOUTP, U0DTRN, Tdo U0RTSN, U1SOUTP, U1DTRN, U1RTSN 1 These are asynchronous signals and the values are provided ...
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IDT 79RC32351 Signal Symbol GPIOP 1 GPIOP[31:0] Tsu1 Thld1 Tdo1 2 GPIOP[35:32] Tsu1 Thld1 Tdo1 1 GPIO[31:0] can be asynchronous signals; the values are provided for ATE (test) only. 2 GPIOP[35:32] are synchronous signals. CLKP GPIOP (output) GPIOP (input) 100MHz ...
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IDT 79RC32351 Signal Symbol EJTAG and JTAG JTAG_TCK Tperiod1 Thigh1,Tlow1 Trise1,Tfall1 1 EJTAG_DCLK Tperiod2 Thigh2,Tlow2 Trise2,Tfall2 JTAG_TMS, JTAG_TDI, Tsu3 JTAG_TRST_N Thld3 JTAG_TDO Tdo4 Tdo5 JTAG_TRST_N Tpw6 Tsu6 EJTAG_PCST[2:0] Tdo7 1. EJTAG_DCLK is equal to the internal CPU pipeline clock. 2. ...
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IDT 79RC32351 Table 14 shows the pin numbering for the Standard EJTAG connector. All the even numbered pins are connected to ground. Multiplexing of pin functions should be considered when connecting For details on using the JTAG connector, see the ...
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IDT 79RC32351 Phase-Locked Loop (PLL) The processor aligns the pipeline clock, PClock, to the master input clock (CLKP) by using an internal phase-locked loop (PLL) circuit that gener- ates aligned clocks. Inherently, PLL circuits are only capable of generating aligned ...
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IDT 79RC32351 Power-on RampUp The 2.5V core supply (and 2.5V V PLL supply) can be fully powered without the 3.3V I/O supply. However, the 3.3V I/O supply cannot exceed the cc 2.5V core supply by more than 1 volt during ...
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IDT 79RC32351 USB Electrical Characteristics Parameter USB Interface V Differential Input Sensitivity di V Differential Input Common Mode cm Range V Single ended Receiver Threshold se C Transceiver Capacitance in I Hi-Z State Data Line Leakage li USB Upstream/Downstream Port ...
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IDT 79RC32351 Power Curve The following graph contains a power curve that shows power consumption at various bus frequencies. Note: The system clock (CLKP) can be multiplied obtain the CPU pipeline clock (PClock) speed. ...
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IDT 79RC32351 Package Pin-out — 208-Pin PQFP The following table lists the pin numbers and signal names for the RC32351. Pin Function Alt 1 ATMOUTP[0] 2 ATMOUTP[1] 3 ATMINP[02] 4 ATMOUTP[2] 5 Vss 6 ATMOUTP[3] 7 ATMINP[03] 8 ATMOUTP[4] 9 ...
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IDT 79RC32351 Pin Function Alt 38 Vcc Core 39 GPIOP[09 GPIOP[10 GPIOP[11 GPIOP[12 Vcc I/O 44 GPIOP[13 Vss 46 GPIOP[14] 47 GPIOP[15] 48 GPIOP[35] 49 GPIOP[34] 50 GPIOP[33] 51 GPIOP[32] ...
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IDT 79RC32351 Package Drawing - 208-pin QFP May 25, 2004 ...
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IDT 79RC32351 Package Drawing - page two May 25, 2004 ...
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IDT 79RC32351 Ordering Information YY XXXX 79RCXX Product Operating Device Type Type Voltage Valid Combinations 79RC32T351 -100DH 79RC32T351 -133DH CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 999 A Temp range/ Package Speed 208-pin QFP package, Commercial ...