IDT79RC32T355-133DH IDT, Integrated Device Technology Inc, IDT79RC32T355-133DH Datasheet
IDT79RC32T355-133DH
Specifications of IDT79RC32T355-133DH
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IDT79RC32T355-133DH Summary of contents
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Features List ◆ RC32300 32-bit Microprocessor – Enhanced MIPS-II ISA – Enhanced MIPS-IV cache prefetch instruction – DSP Instructions – MMU with 16-entry TLB – 8KB Instruction Cache, 2-way set associative – 2KB Data Cache, 2-way set associative – Per ...
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IDT 79RC32355 ◆ USB – Revision 1.1 compliant – USB slave device controller th – Supports a 6 USB endpoint – Full speed operation at 12 Mb/s – Supports control, interrupt, bulk and isochronous endpoints – Supports USB remote wakeup ...
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IDT 79RC32355 Device Overview The RC32355 is a “System on a Chip” which contains a high perfor- mance 32-bit microprocessor. The microprocessor core is used exten- sively at the heart of the device to implement the most needed functionalities in ...
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IDT 79RC32355 Thermal Considerations The RC32355 consumes less than 2.5 W peak power guaran- teed in a ambient temperature range of 0° to +70° C for commercial temperature devices and - 40° to +85° for industrial temperature devices. ...
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IDT 79RC32355 Pin Description Table The following table lists the functions of the pins provided on the RC32355. Some of the functions listed may be multiplexed onto the same pin. To define the active polarity of a signal, a suffix ...
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IDT 79RC32355 Name Type I/O Type RWN O High Drive Read or Write. This signal indicates if the transaction on the memory and peripheral bus is a read transaction or a write transaction. A high level indicates a read from ...
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IDT 79RC32355 Name Type I/O Type TDMTEN O Low Drive TDM External Buffer Enable. This signal controls an external tri-state buffer output enable connected to the TDM output data, TDMDOP asserted low when the RC32355 is driving data ...
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IDT 79RC32355 Name Type I/O Type GPIOP[17] I/O High Drive General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function: Memory and peripheral bus chip select, CSN[5]. GPIOP[18] I/O Low Drive General Purpose I/O. ...
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IDT 79RC32355 Name Type I/O Type DMAREQN I STI External DMA Device Request. The external DMA device asserts this pin low to request DMA service. Primary function: General purpose I/O, GPIOP[18]. At reset, this pin defaults to primary function GPIOP[18]. ...
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IDT 79RC32355 Name Type I/O Type JTAG_TMS I STI JTAG Mode Select. This input signal is decoded by the tap controller to control test operation. This signal requires an external resistor, listed in Table 16. EJTAG_PCST[0] O Low Drive PC ...
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IDT 79RC32355 Name Type I/O Type DMAP[2] O Low Drive Active DMA channel code. DMA debug enable is selected during reset using the boot configuration and overrides the selection of the Primary and Alternate functions. Primary function: General Purpose I/O, ...
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IDT 79RC32355 Name Type I/O Type U1CTSN I STI UART channel 1 clear to send. Primary function: General Purpose I/O, GPIOP[13]. At reset, this pin defaults to primary function GPIOP[13] if ICE Interface enable is not selected during reset using ...
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IDT 79RC32355 Signal MDATA[11] Hold SYSCLKP Constant. For systems that do not require a SYSCLKP output and can instead use CLKP, setting this bit to a one causes the SYSCLKP output to be held at a constant level. This may ...
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IDT 79RC32355 Logic Diagram The following Logic Diagram shows the primary pin functions of the RC32355. SYSCLKP COLDRSTN RSTN USBDP USBDN USBCLKP MIIRXDP[3:0] MIIRXDVP MIIRXERP MIIRXCLKP MIICRSP MIICOLP MIITXDP[3:0] MIITXENP MIITXERP MIITXCLKP MIIMDCP MIIMDIOP JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO VccCore VccI/O ...
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IDT 79RC32355 Clock Parameters (Ta = 0°C to +70°C Commercial -40°C to +85°C Industrial, Vcc I/O = +3.3V±5%,V Parameter 1 Internal CPU pipeline clock 2,3,4 CLKP 1 The CPU pipeline clock speed is selected during cold reset by ...
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IDT 79RC32355 AC Timing Definitions Below are examples of the AC timing characteristics used throughout this document. clock Output signal 1 Output signal 2 Input Signal 1 Signal Symbol Tperiod Clock period. Tlow Clock low. Amount of time the clock ...
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IDT 79RC32355 AC Timing Characteristics (Ta = 0°C to +70°C Commercial -40°C to +85°C Industrial, Vcc I/O = +3.3V±5%,V Reference Signal Symbol Reset and System COLDRSTN Tpw1 Trise1 1 RSTN Tdo2 CLKP rising MDATA[15:0] Thld3 COLDRSTN Boot Configuration ...
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IDT 79RC32355 2 1 CLKP SYSCLKP COLDRSTN Tdo2 RSTN MDATA[31:0] BDIRN BOEN[0] >= 100 ms Tpw1 1. COLDRSTN asserted by external logic. 2. The RC32355 asserts RSTN, asserts BOEN[0] low, drives BDIRN low, and tri-states the data bus in response. ...
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IDT 79RC32355 Signal Symbol Memory and Peripheral Bus - SDRAM Access MDATA[31:0] Tsu1 Thld1 Tdo1 Tdz1 Tzd1 MADDR[20:2], Tdo2 BWEN[3:0] CASN, RASN, Tdo3 SDCSN[1:0], SDWEN CKENP Tdo4 BDIRN Tdo5 BOEN[1:0] Tdo6 SYSCLKP rising Tdo7 SDCLKINP Tperiod8 Thigh8,Tlow8 Trise8,Tfall8 Tdelay8 Table ...
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IDT 79RC32355 Signal Symbol Memory and Peripheral Bus - Device Access MDATA[31:0] Tsu1 Thld1 Tdo1 Tdz1 Tzd1 WAITACKN, BRN Tsu Thld MADDR[21:0] Tdo2 Tdz2 Tzd2 MADDR[25:22] Tdo3 Tdz3 Tzd3 BDIRN, BOEN[0] Tdo4 Tdz4 Tzd4 BGN, BWEN[3:0], OEN, Tdo5 RWN Tdz5 ...
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IDT 79RC32355 CLKP SYSCLKP Tdo2 MADDR[21:0] Tdo2 BWEN[3:0] 1111 Tdo3 CMD[2:0]* NOP READ Tdo3 SDCSN[1:0] 11 Chip-Sel Tdo5 BDIRN Tdo6 11 BOEN[1:0] Tdz1 MDATA[31:0] SDCLKINP * NOTE: CMD[2:0] = {RASN, CASN, SDWEN} Figure 8 Memory and Peripheral Bus AC Timing ...
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IDT 79RC32355 CLKP SYSCLKP MADDR[21:0] BWEN[3:0] 1111 CMD[2:0]* NOP SDCSN[1:0] 11 BDIRN BOEN[1:0] 11 MDATA[31:0] * NOTE: CMD[2:0] = {RASN, CASN, SDWEN} Figure 10 Memory and Peripheral Bus AC Timing Waveform - SDRAM Write Access SDRAM samples Tdo2 write data ...
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IDT 79RC32355 CLKP MADDR[21:0] MADDR[25:22] RWN CSN[3:0] BWEN[3:0] OEN Tdz1 MDATA[31:0] Tdo4 BDIRN BOEN[0] WAITACKN Figure 11 Memory and Peripheral Bus AC Timing Waveform - Device Read Access Tdo2 Addr[21:0] Tdo3 Addr[25:22] Tdo6 1111 Tdo5 RC32355 samples read data Tdo4 ...
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IDT 79RC32355 CLKP MADDR[21:0] MADDR[25:22] RWN CSNx BWEN[3:0] 1111 OEN MDATA[31:0] BDIRN BOEN[0] WAITACKN Figure 12 Memory AC and Peripheral Bus Timing Waveform - Device Write Access Tdo2 Addr[21:0] Tdo3 Addr[25:22] Tdo5 Tdo6 Tdo5 Byte Enables Tdo1 Data Tdo4 24 ...
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IDT 79RC32355 Signal Symbol 1,2 Ethernet MIIRXCLKP, MIITXCLKP Tperiod1 Thigh1,Tlow1 Trise1,Tfall1 MIIRXCLKP, MIITXCLKP Tperiod1 Thigh1,Tlow1 Trise1,Tfall1 MIIRXDP[3:0], Tsu2 MIIRXDVP, MIIRXERP Thld2 MIITXDP[3:0], MIITXENP, Tdo3 MIITXERP MIIMDCP Tperiod4 Thigh4,Tlow4 Trise4 Tfall4 MIIMDIOP Tsu5 Thld5 Tdo5 1 Ethernet clock (MIIRXCLKP and MIITXCLKP) ...
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IDT 79RC32355 MIIRXDVP, MIIRXDP[3:0], MIIRXERP MIITXENP, MIITXDP[3:0], MMTXERP MIIRXCLKP Thld2 Tsu2 MIITXCLKP Tdo3 MIIMDCP Tdo5 MIIMDIOP (output) MIIMDIOP (input) Figure 13 Ethernet AC Timing Waveform Thigh1 Tlow1 Tlow1 Tperiod1 Thigh1 Tlow1 Tlow1 Tperiod1 Tdo3 Tlow4 Tlow4 Thigh4 ...
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IDT 79RC32355 Signal Symbol 1, 2 ATM Interface, Utopia Mode 1 RXCLKP, TXCLKP Tperiod1 Thigh1,Tlow1 Trise1,Tfall1 1 RXCLKP, TXCLKP Tperiod1 Thigh1,Tlow1 Trise1,Tfall1 RXCLKP, TXCLKP Tperiod1 Thigh,Tlow1 Trise1,Tfall1 TXFULLN Tsu2 Thld2 TXDATA[7:0], TXSOC, Tdo3 TXENBN, TXADDR[1:0] RXDATA[7:0], RXEMP- Tsu4 TYN, RXSOC ...
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IDT 79RC32355 TXDATA,TXSOC,TXENB,TXADDR RXDATA, RXEMPTY, RXSOC RXADDR, RXENB O0CLKP, O1CLKP O0DP, O0FRMP O1DP, O1FRMP I0CLKP, I1CLKP TXCLKP Tsu2 Thld2 TXFULL RXCLKP Tsu4 Thld4 Tdo5 Tdo7 Tdo8 Tsu9 Thld9 I0DP Thld10 Tsu10 I1DP Figure 14 ATM AC Timing Waveform 28 of ...
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IDT 79RC32355 ATM Pin Name ATMINP[0] ATMINP[1] ATMINP[2] ATMINP[3] ATMINP[4] ATMINP[5] ATMINP[6] ATMINP[7] ATMINP[8] ATMINP[9] ATMINP[10] ATMINP[11] ATMIOP[0] ATMIOP[1] ATMOUTP[0] ATMOUTP[1] ATMOUTP[2] ATMOUTP[3] ATMOUTP[4] ATMOUTP[5] ATMOUTP[6] ATMOUTP[7] ATMOUTP[8] ATMOUTP[9] GPIOP[22] GPIOP[23] GPIOP[24] GPIOP[25] Utopia Level 1 Utopia Level 2 RXDATA[0] ...
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IDT 79RC32355 Signal Symbol TDM 1 TDMCLKP Tperiod1 Thigh1 Tlow1 Trise1 Tfall1 TDMFP Tsu2 Thld2 Tdo2 TDMDIP Tsu3 Thld3 TDMDOP Tdo4 Tdz4 Tzd4 TDMTEN Tdo5 1 The rising or falling edge of TDMCLKP is used as the reference clock edge ...
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IDT 79RC32355 TDMCLKP Tsu2 TDMFP TDMDOP TDMDIP TDMTEN Thld2 Tdo4 Tdo4 Thld3 Tsu3 Tdo5 Figure 16 TDM AC Timing Waveform, Slave Mode Tdo5 May 25, 2004 ...
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IDT 79RC32355 Signal Symbol USB 1 USBCLKP Tperiod1 Thigh1,Tlow1 Trise1,Tfall1 Tjitter1 USBDN, USBDP Trise2 Tfall2 USBDN and USBDP Rise and Fall Time Matching Data valid period Tstate Skew between USBDN and USBDP Source data jitter Receive data jitter Source EOP ...
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IDT 79RC32355 USBCLKP Tjitter1 USBDN 10% USBDP Tfdrate USBDN USBDP Signal Symbol UART U0SINP, U0RIN, U0DCDN, U0DSRN, U0CTSN, U1SINP, Thld U1DSRN, U1CTSN U0SOUTP, U0DTRN, U0RTSN, U1SOUTP, U1DTRN, U1RTSN 1 These are asynchronous signals and the values are provided for ATE ...
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IDT 79RC32355 Signal Symbol SCLP Frequency Thigh1 Tlow1 Trise1 Tfall1 SDAP Tsu2 Thld2 Trise2 Tfall2 Start or repeated start condition Tsu3 Thld3 Stop condition Tsu4 Bus free time between a stop and Tdelay5 start condition SCLP ...
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IDT 79RC32355 SDAP Thld3 SCLP Signal Symbol GPIOP 1 GPIOP[31:0] Tsu1 Thld1 Tdo1 2 GPIOP[35:32] Tsu1 Thld1 Tdo1 1 GPIOP[31:0] are controlled through the GPIO interface. GPIO[31:0] are asynchronous signals, the values are provided for ATE (test) only. 2 GPIOP[35:32] ...
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IDT 79RC32355 Signal Symbol EJTAG and JTAG JTAG_TCK Tperiod1 Thigh1, Tlow1 Trise1, Tfall1 1 EJTAG_DCLK Tperiod2 Thigh2, Tlow2 Trise2, Tfall2 JTAG_TMS, JTAG_TDI, Tsu3 JTAG_TRST_N Thld3 JTAG_TDO Tdo4 Tdo5 JTAG_TRST_N Tpw6 Tsu6 EJTAG_PCST[2:0] Tdo7 1. EJTAG_DCLK is equal to the internal ...
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IDT 79RC32355 Table 16 shows the pin numbering for the Standard EJTAG connector. All the even numbered pins are connected to ground. Multiplexing of pin functions should be considered when connecting For details on using the JTAG connector, see the ...
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IDT 79RC32355 Phase-Locked Loop (PLL) The processor aligns the pipeline clock, PClock, to the master input clock (CLKP) by using an internal phase-locked loop (PLL) circuit that gener- ates aligned clocks. Inherently, PLL circuits are only capable of generating aligned ...
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IDT 79RC32355 Power-on RampUp The 2.5V core supply (and 2.5V V PLL supply) can be fully powered without the 3.3V I/O supply. However, the 3.3V I/O supply cannot exceed the cc 2.5V core supply by more than 1 volt during ...
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IDT 79RC32355 USB Electrical Characteristics Parameter USB Interface V Differential Input Sensitivity di V Differential Input Common Mode cm Range V Single ended Receiver Threshold se C Transceiver Capacitance in I Hi-Z State Data Line Leakage li USB Upstream/Downstream Port ...
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IDT 79RC32355 Power Curve The following graph contains a power curve that shows power consumption at various bus frequencies. Note: The system clock (CLKP) can be multiplied obtain the CPU pipeline clock (PClock) speed. ...
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IDT 79RC32355 Package Pin-out — 208-Pin PQFP The following table lists the pin numbers and signal names for the RC32355. Pin Function Alt 1 ATMOUTP[0] 2 ATMOUTP[1] 3 ATMINP[02] 4 ATMOUTP[2] 5 Vss 6 ATMOUTP[3] 7 ATMINP[03] 8 ATMOUTP[4] 9 ...
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IDT 79RC32355 Pin Function Alt 35 GPIOP[07 ATMINP [11] 37 GPIOP[08 Vcc Core 39 GPIOP[09 GPIOP[10 GPIOP[11 GPIOP[12 Vcc I/O 44 GPIOP[13 Vss 46 GPIOP[14] 1 ...
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IDT 79RC32355 Alternate Pin Functions Pin Primary 20 GPIOP[00] U0SOUTP 21 GPIOP[01] U0SINP 23 GPIOP[02] U0RIN 24 GPIOP[03] U0DCRN 27 GPIOP[04] U0DTRN 28 GPIOP[05] U0DSRN 33 GPIOP[06] U0RTSN 35 GPIOP[07] U0CTSN 37 GPIOP[08] U1SOUTP 39 GPIOP[09] U1SINP 40 GPIOP[10] U1DTRN ...
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IDT 79RC32355 Package Drawing - 208-pin QFP May 25, 2004 ...
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IDT 79RC32355 Package Drawing - page two May 25, 2004 ...
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IDT 79RC32355 Ordering Information YY XXXX 79RCXX Product Operating Device Type Type Voltage Valid Combinations 79RC32T355 -133DH, 150DH, 180DH 79RC32T355 -133DHI, 150DHI CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 999 A Temp range/ Package Speed 208-pin QFP package, ...