IDT79RC32H434-300BCGI IDT, Integrated Device Technology Inc, IDT79RC32H434-300BCGI Datasheet
IDT79RC32H434-300BCGI
Specifications of IDT79RC32H434-300BCGI
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IDT79RC32H434-300BCGI Summary of contents
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Device Overview Device Overview Device Overview Device Overview The RC32434 is a member of the IDT™ Interprise™ family of PCI integrated communications processors. It incorporates a high perfor- mance CPU core and a number of on-chip peripherals. The integrated processor ...
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IDT RC32434 Memory and Peripheral Device Controller – Provides “glueless” interface to standard SRAM, Flash, ROM, dual-port memory, and peripheral devices – Demultiplexed address and data buses: 8-bit data bus, 26-bit address bus, 4 chip selects, control for external data ...
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IDT RC32434 DMA Controller DMA Controller DMA Controller DMA Controller The DMA controller consists of 6 independent DMA channels, all of which operate in exactly the same manner. The DMA controller off-loads the CPU core from moving data among the ...
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IDT RC32434 Description Table in Description Table in Description Table in Description Table The following table lists the functions of the pins provided on the RC32434. Some of the functions listed may be multiplexed onto ...
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IDT RC32434 Signal DDRCKP DDRCSN DDRDATA[15:0] DDRDM[1:0] DDRDQS[1:0] DDRRASN DDRVREF DDRWEN PCI Bus PCIAD[31:0] PCICBEN[3:0] PCICLK PCIDEVSELN PCIFRAMEN PCIGNTN[3:0] PCIIRDYN Type Name/Description O DDR Positive DDR clock. This signal is the positive clock of the differential DDR clock pair. O ...
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IDT RC32434 Signal PCILOCKN PCIPAR PCIPERRN PCIREQN[3:0] PCIRSTN PCISERRN PCISTOPN PCITRDYN General Purpose Input/Output GPIO[0] GPIO[1] GPIO[2] GPIO[3] Type Name/Description I/O PCI Lock. This signal is asserted by an external bus master to indicate that an exclusive operation is occurring. ...
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IDT RC32434 Signal GPIO[4] GPIO[5] GPIO[6] GPIO[7] GPIO[8] GPIO[9] GPIO[10] GPIO[11] GPIO[12] GPIO[13] SPI Interface SCK Type Name/Description I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: MADDR[22] Alternate function: ...
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IDT RC32434 Signal SDI SDO Bus Interface SCL SDA Ethernet Interfaces MIICL MIICRS MIIRXCLK MIIRXD[3:0] MIIRXDV MIIRXER MIITXCLK MIITXD[3:0] MIITXENP MIITXER MIIMDC MIIMDIO EJTAG / JTAG JTAG_TMS Type Name/Description I/O Serial Data Input. This signal is used ...
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IDT RC32434 Signal EJTAG_TMS JTAG_TRST_N JTAG_TCK JTAG_TDO JTAG_TDI System CLK EXTBCV EXTCLK COLDRSTN RSTN Pin Characteristics Pin Characteristics Pin Characteristics Pin Characteristics Note: Some input pads of the RC32434 do not contain internal pull-ups or pull-downs. Unused inputs should be ...
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IDT RC32434 Function Pin Name Memory and Peripheral BDIRN Bus BOEN WEN CSN[3:0] MADDR[21:0] MDATA[7:0] OEN RWN WAITACKN DDR Bus DDRADDR[13:0] DDRBA[1:0] DDRCASN DDRCKE DDRCKN DDRCKP DDRCSN DDRDATA[15:0] DDRDM[1:0] DDRDQS[1:0] DDRRASN DDRVREF DDRWEN PCI Bus Interface PCIAD[31:0] PCICBEN[3:0] PCICLK PCIDEVSELN ...
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IDT RC32434 Function Pin Name Ethernet Interfaces MIICL MIICRS MIIRXCLK MIIRXD[3:0] MIIRXDV MIIRXER MIITXCLK MIITXD[3:0] MIITXENP MIITXER MIIMDC MIIMDIO EJTAG / JTAG JTAG_TMS EJTAG_TMS JTAG_TRST_N JTAG_TCK JTAG_TDO JTAG_TDI System CLK EXTBCV EXTCLK COLDRSTN RSTN 1. External pull-up required in most ...
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IDT RC32434 Boot Configuration Vector Boot Configuration Vector Boot Configuration Vector Boot Configuration Vector The encoding of the boot configuration vector is described in Table 3, and the vector input is illustrated in Figure 4. The value of the boot ...
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IDT RC32434 Signal MADDR[11] MADDR[13:12] MADDR[15:14] Name/Description Disable Watchdog Timer. When this bit is set, the watchdog timer is disabled follow- ing a cold reset. 0x0 - Watchdog timer enabled 0x1 - Watchdog timer disabled Reserved. These pins must be ...
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IDT RC32434 ogic Diagram — ogic Diagram — ogic Diagram — ogic Diagram — RC32434 RC32434 RC32434 RC32434 System Signals Ethernet EJTAG / JTAG Signals General Purpose I/O SPI 2 I C-Bus CLK COLDRSTN RSTN EXTCLK ...
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IDT RC32434 AC Timing Definitions AC Timing Definitions AC Timing Definitions AC Timing Definitions Below are examples of the AC timing characteristics used throughout this document. clock Output signal 1 Output signal 2 Input Signal 1 Signal 1 Signal 2 ...
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IDT RC32434 ystem Clock Parameters ystem Clock Parameters ystem Clock Parameters ystem Clock Parameters (Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 15 and 16.) Parameter Symbol Reference ...
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IDT RC32434 AC Timing Characteristics AC Timing Characteristics AC Timing Characteristics AC Timing Characteristics (Values given below are based on systems running at recommended operating temperatures and supply voltages, shown in Tables 15 and 16.) Reference Signal Symbol Edge Reset ...
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IDT RC32434 1 2 CLK COLDRSTN RSTN MADDR[15:0] MADDR[21:16] EXTCLK EXTBCV * COLDRSTN sampled negated (high) by the RC32434 1. EXTBCV is asserted (i.e., pulled-up). COLDRSTN is asserted by external logic. The RC32434 responds by immediately tri-stating the bottom 16-bits ...
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IDT RC32434 CLK COLDRSTN RSTN MDATA[7:0] Mem Control Signals 1. Warm reset condition caused by assertion of RSTN by an external agent. 2. The RC32434 tri-states the data bus, MDATA[7:0], negates all memory control signals, and itself asserts RSTN. The ...
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IDT RC32434 DDRCKP DDRCKN DDRCSN DDRADDR[13:0] 1 NOP DDRCMD DDRCKE DDRBA[1:0] DDRDM[1:0] DDRDQSx (ideal) 2 DDRDATA[15:0] (ideal) DDRDQSx (min) 2 DDRDATA[15:0] DDRDQSx (max) 2 DDRDATA[15:0] 1 DDRCMD contains DDRRASN, DDRCASN and DDRWEN. 2 DDRDATA is either 32-bits or 16-bits wide ...
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IDT RC32434 DDRCKP DDRCKN DDRCSN DDRADDR[13:0] 1 NOP DDRCMD DDRCKE DDRBA[1:0] DDRDQSx DDRDM[1:0] DDRDQSx 2 DDRDATA[15:0] 1 DDRCMD contains DDRRASN, DDRCASN and DDRWEN. 2 DDRDATA is either 32-bits or 16-bits wide depending on the DBW control bit in DDRC Register ...
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IDT RC32434 Reference Signal Symbol Edge MDATA[7:0] Tsu_8c EXTCLK rising Thld_8c Tdo_8c 2 Tdz_8c 2 Tzd_8c 3 EXTCLK Tper_8d none BDIRN Tdo_8e EXTCLK rising 2 Tdz_8e 2 Tzd_8e BOEN Tdo_8f EXTCLK rising 2 Tdz_8f 2 Tzd_8f 4 WAITACKN Tsu_8h EXTCLK ...
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IDT RC32434 EXTCLK MADDR[21:0] MADDR[25:22] RWN CSN[3:0] WEN OEN Tdz_8c MDATA[7:0] Tdo_8e BDIRN BOEN WAITACKN Figure 8 Memory and Peripheral Bus AC Timing Waveform — Read Access Tper_8d Tdo_8a Addr[21:0] Tdo_8b Addr[25:22] Tdo_8i 1111 Tdo_8k RC32434 samples read data Tdo_8f ...
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IDT RC32434 EXTCLK MADDR[21:0] MADDR[25:22] RWN CSN[3:0] 1111 WEN OEN MDATA[7:0] BDIRN BOEN WAITACKN Figure 9 Memory and Peripheral Bus AC Timing Waveform — Write Access Tdo_8a Addr[21:0] Tdo_8b Addr[25:22] Tdo_8j Tdo_8i Tdo_8l Byte Enables Tdo_8c Data Tdo_8f 24 of ...
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IDT RC32434 Reference Signal Symbol Edge Ethernet MIIMDC Tper_9a None Thigh_9a, Tlow_9a MIIMDIO Tsu_9b MIIMDC rising Thld_9b 1 Tdo_9b Ethernet — MII Mode MIIRXCLK, Tper_9c None 2 MIITXCLK Thigh_9c, Tlow_9c Trise_9c, Tfall_9c MIIRXCLK, Tper_9d None 2 MIITXCLK Thigh_9d, Tlow_9d Trise_9d, ...
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IDT RC32434 MIIMDIO (output) MIIMDIO (input) MIIRXDV, MIIRXD[3:0], MIIRXER MIITXEN, MIITXD[3:0], MIITXER RMII CRS_DV, RMII RXER Thigh_9a Tper_9a MIIMDC Tdo_9b Tsu_9b Tper_9d MIIRXCLK Thld_9e Tsu_9e Tper_9d MIITXCLK Tdo_9f Tper_9i RMII REFCLK Tdo_9j Tdo_9j RMII TXEN, RMII TXD[1:0] Tper_9i Thigh_9i RMII ...
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IDT RC32434 Reference Signal Symbol Edge 1 PCI 2 PCICLK Tper_10a none Thigh_10a, Tlow_10a Tslew_10a PCIAD[31:0], Tsu_10b PCICLK rising PCIBEN[3:0], Thld_10b PCIDEVSELN, PCIFRA- Tdo_10b MEN,PCIIR- 3 Tdz_10b DYN, PCILOCKN, 3 Tzd_10b PCIPAR, PCI- PERRN, PCIS- TOPN, PCITRDY PCIGNTN[3:0], Tsu_10c PCICLK ...
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IDT RC32434 PCICLK Bussed output Point to point output Bussed input Point to point input COLDRSTN PCIRSTN (output) RSTN Note: During and after cold reset, PCIRSTN is tri-stated and requires a pull-down to reach a low state. After the PCI ...
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IDT RC32434 CLKP PCIRSTN (input) RSTN MDATA[15:0] PCI bus signals Reference Signal Symbol SCL Frequency none Thigh_12a, Tlow_12a Trise_12a Tfall_12a SDA Tsu_12b SCL rising Thld_12b Trise_12b Tfall_12b Start or repeated start Tsu_12c SDA falling condition Thld_12c ...
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IDT RC32434 Reference Signal Symbol Start or repeated start Tsu_12c SDA falling condition Thld_12c Stop condition Tsu_12d SDA rising Bus free time between Tdelay_12e a stop and start condi- tion 1. 2 For more information, see the I C-Bus specification ...
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IDT RC32434 Reference Signal Symbol Edge 1 SPI SCK Tper_15a None Thigh_15a, Tlow_15a SDI Tsu_15b SCK rising or falling Thld_15b SDO Tdo_15c SCK rising or falling SCK, SDI, Tpw_15e None SDO 1. In SPI mode, the SCK period and sampling ...
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IDT RC32434 Reference Signal Symbol Edge EJTAG and JTAG JTAG_TCK Tper_16a none Thigh_16a, Tlow_16a 1 JTAG_TMS , Tsu_16b JTAG_TCK JTAG_TDI rising Thld_16b JTAG_TDO Tdo_16c JTAG_TCK fall- ing 2 Tdz_16c 2 JTAG_TRST_ Tpw_16d none N 1 EJTAG_TMS Tsu_16e JTAG_TCK rising Thld_6e ...
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IDT RC32434 JTAG_TCK JTAG_TDI JTAG_TMS EJTAG_TMS JTAG_TDO JTAG_TRST_N The IEEE 1149.1 specification requires that the JTAG and EJTAG TAP controllers be reset at power-up whether or not the interfaces are used for a boundary scan or a probe. Reset can ...
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IDT RC32434 Using the EJTAG Probe Using the EJTAG Probe Using the EJTAG Probe Using the EJTAG Probe In Figure 20, the pull-up resistors for JTAG_TDO and RST*, the pull-down resistor for JTAG_TRST_N, and the series resistor for JTAG_TDO must ...
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IDT RC32434 Recommended Operating Supply Voltages Recommended Operating Supply Voltages Recommended Operating Supply Voltages Recommended Operating Supply Voltages Symbol V Common ground ss V PLL PLL ground ss V I/O I/O supply except for SSTL_2 cc V SI/O (DDR) I/O ...
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IDT RC32434 Power-on Sequence Power-on Power-on Power-on Sequence Sequence Sequence Three power-on sequences are given below. Sequence #1 is recommended because it will prevent I/O conflicts and will also allow the input signals to propagate when the I/O powers are ...
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IDT RC32434 ower Consumptio ower Consumptio ower Consumption ower Consumptio Parameter 266MHz Typ. I I/O 215 cc I SI/O (DDR Core, Normal 325 cc I PLL mode cc Standby 220 ...
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IDT RC32434 DC Electrical Characteristics DC Electrical Characteristics DC Electrical Characteristics DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 15. Note: See Table 2, Pin Characteristics, for a complete I/O listing. Para- ...
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IDT RC32434 AC Test Conditions AC Test Conditions AC Test Conditions AC Test Conditions RC32434 Output . 50 Value Parameter SSTL I/O Input pulse levels 0 to 2.5 Input rise/fall 0.8 Input reference level 0.5(VccSI/O) Output reference levels 1.25 AC ...
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IDT RC32434 Absolute Maximum Ratings Absolute Maximum Ratings Absolute Maximum Ratings Absolute Maximum Ratings Symbol V I SI/O (DDR Core CC V PLL CC V APLL CC VinI/O VinSI Industrial T a Commercial T ...
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IDT RC32434 ackage Pin-out — ackage Pin-out — 256-BGA S ackage Pin-out — ackage Pin-out — 256-BGA Signal Pinout for 256-BGA S 256-BGA S The following table lists the pin numbers, signal names, and number of ...
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IDT RC32434 Pin Function Alt Pin C2 BDIRN G2 C3 COLDRSTN G3 C4 WEN G4 C5 MDATA[ MDATA[ GPIO[ MADDR[21 MADDR[18] G9 C10 MADDR[14] G10 C11 JTAG_TMS G11 C12 V APLL ...
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IDT RC32434 RC32434 Alternate Signal Functions RC32434 Alternate Signal Functions RC32434 Alternate Signal Functions RC32434 Alternate Signal Functions Pin A7 GPIO[7] A8 GPIO[4] B8 GPIO[5] C7 GPIO[6] H3 GPIO[0] H4 GPIO[1] J1 GPIO[3] RC32434 Power P RC32434 P ower Pins ...
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IDT RC32434 RC32434 G RC32434 G RC32434 G RC32434 Ground Pins round Pins round Pins round Pins C32434 S C32434 Signals Listed Alphabetically ignals Listed Alphabetically C32434 S C32434 S ignals Listed Alphabetically ignals Listed Alphabetically ...
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IDT RC32434 Signal Name DDRADDR[0] DDRADDR[1] DDRADDR[2] DDRADDR[3] DDRADDR[4] DDRADDR[5] DDRADDR[6] DDRADDR[7] DDRADDR[8] DDRADDR[9] DDRADDR[10] DDRADDR[11] DDRADDR[12] DDRADDR[13] DDRBA[0] DDRBA[1] DDRCASN DDRCKE DDRCKN DDRCKP DDRCSN DDRDATA[0] DDRDATA[1] DDRDATA[2] DDRDATA[3] DDRDATA[4] DDRDATA[5] DDRDATA[6] DDRDATA[7] DDRDATA[8] DDRDATA[9] DDRDATA[10] DDRDATA[11] DDRDATA[12] DDRDATA[13] DDRDATA[14] ...
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IDT RC32434 Signal Name DDRDATA[15] DDRDM[0] DDRDM[1] DDRDQS[0] DDRDQS[1] DDRRASN DDRVREF DDRWEN EJTAG_TMS EXTBCV EXTCLK GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] GPIO[8] GPIO[9] GPIO[10] GPIO[11] GPIO[12] GPIO[13] JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRSTN I/O Type Location I/O H13 O ...
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IDT RC32434 Signal Name MADDR[0] MADDR[1] MADDR[2] MADDR[3] MADDR[4] MADDR[5] MADDR[6] MADDR[7] MADDR[8] MADDR[9] MADDR[10] MADDR[11] MADDR[12] MADDR[13] MADDR[14] MADDR[15] MADDR[16] MADDR[17] MADDR[18] MADDR[19] MADDR[20] MADDR[21] MDATA[0] MDATA[1] MDATA[2] MDATA[3] MDATA[4] MDATA[5] MDATA[6] MDATA[7] I/O Type Location O C15 O ...
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IDT RC32434 Signal Name MIICL MIICRS MIIMDC MIIMDIO MIIRXCLK MIIRXD[0] MIIRXD[1] MIIRXD[2] MIIRXD[3] MIIRXDV MIIRXER MIITXCLK MIITXD[0] MIITXD[1] MIITXD[2] MIITXD[3] MIITXENP MIITXER OEN PCIAD[0] PCIAD[1] PCIAD[2] PCIAD[3] PCIAD[4] PCIAD[5] PCIAD[6] PCIAD[7] PCIAD[8] PCIAD[9] PCIAD[10] PCIAD[11] PCIAD[12] PCIAD[13] PCIAD[14] PCIAD[15] PCIAD[16] ...
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IDT RC32434 Signal Name PCIAD[17] PCIAD[18] PCIAD[19] PCIAD[20] PCIAD[21] PCIAD[22] PCIAD[23] PCIAD[24] PCIAD[25] PCIAD[26] PCIAD[27] PCIAD[28] PCIAD[29] PCIAD[30] PCIAD[31] PCIBEN[0] PCIBEN[1] PCIBEN[2] PCIBEN[3] PCICLK PCIDEVSELN PCIFRAMEN PCIGNTN[0] PCIGNTN[1] PCIGNTN[2] PCIGNTN[3] PCIIRDYN PCILOCKN PCIPAR PCIPERRN PCIREQN[0] PCIREQN[1] PCIREQN[2] PCIREQN[3] PCIRSTN PCISERRN ...
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IDT RC32434 Signal Name PCISTOPN PCITRDYN RSTN RWN SCK SCL SDA SDI SDO Vcc APLL Vcc Core Vcc DDR Vcc I/O Vcc PLL Vss Vss APLL Vss PLL WAITACKN WEN Reserved I/O Type Location I/O P8 I/O R8 I/O B2 ...
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IDT RC32434 C32434 P C32434 Package Drawing — C32434 P C32434 P ackage Drawing — ackage Drawing — ackage Drawing — 256-pin 256-pin 256-pin 256-pin CA CA CABGA CA BGA BGA BGA January ...
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IDT RC32434 RC32434 P RC32434 P RC32434 P RC32434 Package Drawing ackage Drawing ackage Drawing ackage Drawing — — — — Page Two Page Two Page Two Page Two January 19, 2006 ...
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IDT RC32434 Ordering Information Ordering Information Ordering Information Ordering Information YY XXXX 79RCXX Product Operating Device Type Type Voltage Valid Combinations Valid Combinations Valid Combinations Valid Combinations 79RC32H434 - 266BC, 300BC, 350BC, 400BC 79RC32H434 - 266BCI, 300BCI, 350BCI CORPORATE HEADQUARTERS ...