IDT79RC32K438-200BB IDT, Integrated Device Technology Inc, IDT79RC32K438-200BB Datasheet - Page 5

• Manufacturer Part Number: IDT79RC32K438-200BB
• Description: IC MPU 32BIT CORE 200MHZ 416-BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Interprise™r

Specifications of IDT79RC32K438-200BB

• Processor Type: MIPS32 32-Bit
• Speed: 200MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 416-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79RC32K438-200BB

IDT 79RC32438
WAITACKN
DDR Bus
DDRADDR[13:0]
DDRBA[1:0]
DDRCASN
DDRCKE
DDRCKN[1:0]
DDRCKP[1:0]
DDRCSN[1:0]
DDRDATA[31:0]
DDRDM[7:0]
DDRDQS[3:0]
DDROEN[3:0]
DDRRASN
Signal
Type
I/O
I/O
O
O
O
O
O
O
O
O
O
O
I
Wait or Transfer Acknowledge. When configured as wait, this signal is
asserted during a memory and peripheral bus transaction to extend the bus
cycle. When configured as a transfer acknowledge, this signal is asserted during
a transaction to signal the completion of the transaction.
DDR Address Bus. 14-bit multiplexed DDR bus address bus. This bus is used
to transfer the addresses to the DDR devices.
DDR Bank Address. These signals are used to transfer the bank address to the
DDRs.
DDR Column Address Strobe. This signal is asserted during DDR transac-
tions.
DDR Clock Enable. The DDR clock enable is asserted during normal DDR
operation. This signal is negated during following a cold reset or during a power
down operation.
DDR Negative DDR clock. These signals are the negative clock of the differen-
tial DDR clock pair. Two copies of this output are provided to reduce signal load-
ing.
DDR Positive DDR clock. These signals are the positive clock of the differen-
tial DDR clock pair. Two copies of this output are provided to reduce signal load-
ing.
DDR Chip Selects. These active low signals are used to select DDR device(s)
on the DDR bus.
DDR Data Bus. 32-bit DDR data bus used to transfer data between the
RC32438 and the DDR devices. Data is transferred on both edges of the clock.
DDR Data Write Enables. Byte data write enables used to enable specific byte
lanes during DDR writes.
DDRDM[0] corresponds to DDRDATA[7:0]
DDRDM[1] corresponds to DDRDATA[15:8]
DDRDM[2] corresponds to DDRDATA[23:16]
DDRDM[3] corresponds to DDRDATA[31:24]
DDRDM[4] corresponds to DDRDATA[39:32]
DDRDM[5] corresponds to DDRDATA[47:40]
DDRDM[6] corresponds to DDRDATA[55:48]
DDRDM[7] corresponds to DDRDATA[54:56]
(Refer to the DDR Data Bus Multiplexing section in Chapter 7 of the RC32438
User Reference Manual.)
DDR Data Strobes. DDR byte data strobes used to clock data between DDR
devices and the RC32438. These strobes are inputs during DDR reads and out-
puts during DDR writes.
DDRDQS[0] corresponds to DDRDATA[7:0].
DDRDQS[1] corresponds to DDRDATA[15:8].
DDRDQS[2] corresponds to DDRDATA[23:16].
DDRDQS[3] corresponds to DDRDATA[31:24].
DDR Bus Switch Output Enables. These pins are used to enable external
data bus switches in systems that support data bus multiplexing.
DDR Row Address Strobe. The DDR row address strobe is asserted during
DDR transactions.
Table 1 Pin Description (Part 2 of 9)
5 of 59
Name/Description
May 25, 2004