IDT79RC64V474-180DZ IDT, Integrated Device Technology Inc, IDT79RC64V474-180DZ Datasheet - Page 5

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IDT79RC64V474-180DZ

Manufacturer Part Number
IDT79RC64V474-180DZ
Description
IC MPU 64BIT EMB 180MHZ 128-QFP
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT79RC64V474-180DZ

Processor Type
RISC 64-Bit
Speed
180MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Other names
79RC64V474-180DZ

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT79RC64V474-180DZ
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
RC64474™ RC64475™
255:18
17:15
14:13
12
11
10:9
7:5
8
4:1
0
Serial
Bit
Reserved
WAdrWData_Del
Write address to write data delay in Master-
Clock cycles.®
Drv_Out
output driver slew rate control. Bit 14 is MSB.
Affects only non-clock outputs.
System interface bus width
TmrIntEn
Disables the timer interrupt on Int*[5]
Non-block write
Selects non-block write type. Bit 10 is MSB.
Clock
Multiplier
MasterClock is multiplied internally to gener-
ate PClock
EndBit
Specifies byte ordering
Writeback data rate
System interface data rate for block writes
only: bit 4 is MSB
Reserved
Description
Table 3 Boot-time Mode Stream
000 → 0 cycles
001 → 1 cycle
010 → 2 cycles
011 → 3 cycles
100 → 4 cycles
101 → 5 cycles
110 → 6 cycles
111 → 7 cycles
Output driver strength:
10 → 100% strength (fastest)
11 → 83% strength
00 → 67% strength
01 → 50% strength (slowest)
0 → 64-bit system interface
1 → 32-bit system interface
0 → Enabled Timer Interrupt
1 → Disabled Timer Interrupt
00 → RC4x00 compatible
01 → Reserved
10 → Pipelined writes
11 → Write re-issue
Clock multiplier:
0 Multiply by 2
1 Multiply by 3
2 Multiply by 4
3 Multiply by 5
4 Multiply by 6
5 Multiply by 7
6 Multiply by 8
7 Reserved
0 → Little endian
1 → Big endian
64-bit:
9:15 Reserved
8 → dxxxdxxxdxxxdxxx
7 → ddxxxxxxddxxxxxx
6 → dxxdxxdxxdxx
5 → ddxxxxddxxxx
4 → ddxxxddxxx
3 → dxdxdxdx
2 → ddxxddxx
1 → ddxddx
0 → dddd
Must be zero
Must be 0
5 of 25
Value & Mode Setting
32-bit:
9:15 Reserved
8 → wxxxwxxxwxxxwxxxwxxxwxxxwxxxwxxx
7 → wwxxxxxxwwxxxxxxwwxxxxxxwwxxxxxx
6 → wxxwxxwxxwxxwxxwxxwxxwxx
5 → wwxxxxwwxxxxwwxxxxwwxxxx
4 → wwxxxwwxxxwwxxxwwxxx
3 → wxwxwxwxwxwxwxwx
2 → wwxxwwxxwwxxwwxx
1 → wwxwwxwwxwwx
0 →Æ wwwwwwww
April 10, 2001

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