IDT79RC64T574-200DZ IDT, Integrated Device Technology Inc, IDT79RC64T574-200DZ Datasheet - Page 7

• Manufacturer Part Number: IDT79RC64T574-200DZ
• Description: IC MPU 64BIT EMB 200MHZ 128-QFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT79RC64T574-200DZ

• Processor Type: RISC 64-Bit
• Speed: 200MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79RC64T574-200DZ

Pin Description Table
Pin Description Table
Pin Description Table
Pin Description Table
79RC64574™ 79RC64575™
The following is a list of system interface pins available on the RC64574/575. Pin names ending with an asterisk (*) are active when low.
System Interface
ExtRqst*
Release*
RdRdy*
WrRdy*
ValidIn*
ValidOut*
SysAD(63:0)
SysADC(7:0)
SysCmd(8:0)
SysCmdP
Clock/Control Interface
SysClock
V
V
CC
SS
P
P
Pin Name
I
O
I
I
I
O
I/O
I/O
I/O
I/O
I
I
I
Type
External request
An external agent asserts ExtRqst* to request use of the System interface. The processor grants the request
by asserting Release*.
Release interface
In response to the assertion of ExtRqst* or a CPU read request, the processor asserts Release* and signals
to the requesting device that the system interface is available.
Read Ready
The external agent asserts RdRdy* to indicate that it can accept a processor read request.
Write Ready
An external agent asserts WrRdy* when it can now accept a processor write request.
Valid Input
Signals that an external agent is now driving a valid address or data on the SysAD bus and a valid command
or data identifier on the SysCmd bus.
Valid Output
Signals that the processor is now driving a valid address or data on the SysAD bus and a valid command or
data identifier on the SysCmd bus.
System address/data bus
A 64-bit address and data bus for communication between the processor and an external agent. In 64 bit
interface mode, during address phases only, SysAd(35:0) contains invalid address information. The remain-
ing SysAD(63:36) pins are not used. The whole 64-bit SysAD(63:0) may be used during the data transfer
phase. For all double-word accesses (read or write), the low-order 3 bits (SysAD[2:0]) will always be output as
zero during the address phase.
In 32-bit interface mode and in the RC64574, SysAD(63:32) is not used, regardless of Endianness. A 32-bit
address and data communication between processor and external agent is performed via SysAD(31:0).
System address/data check bus
An 8-bit bus containing parity check bits for the SysAD bus during data bus cycles.
In 32-bit mode and in the RC64574, SysADC(7:4) is not used. The SysADC(3:0) contains check bits for
SysAD(31:0).
System command/data identifier bus
A 9-bit bus for command and data identifier transmission between the processor and an external agent.
System Command Parity
A single, even-parity bit for the Syscmd bus. This signal is always driven low.
SystemClock
The system clock input establishes the processor and bus operating frequency. It is multiplied internally by
2,3,4,5,6,7, or 8 to generate the pipeline clock (PClock).
Quiet VCC for PLL
Quiet V
Quiet V
Quiet V
CC
SS
SS
for PLL
for the internal phase locked loop.
for the internal phase locked loop.
Table 5 Pin Descriptions (Page 1 of 2)
7 of 28
Description
December 14, 2001