IDT79RV4700-100GH IDT, Integrated Device Technology Inc, IDT79RV4700-100GH Datasheet - Page 11

• Manufacturer Part Number: IDT79RV4700-100GH
• Description: IC MPU 64BIT RISC 100MHZ 179-PGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT79RV4700-100GH

• Processor Type: RISC 64-Bit
• Speed: 100MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 179-PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79RV4700-100GH

Pin Description
asterisk are active when low. Boundary scan is not supported.
IDT79R4700
The table below provides a list of interface, interrupt and miscellaneous pins that are available on the RC4700. Note that signals marked with an
System Interface
ExtRqst*
Release*
RdRdy*
WrRdy*
ValidIn*
ValidOut*
SysAD(63:0)
SysADC(7:0)
SysCmd(8:0)
SysCmdP
Clock/Control Interface
MasterClock
MasterOut
RClock(1:0)
TClock(1:0)
IOOut
IOIn
SyncOut
SyncIn
Fault*
Pin Name
Type
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
External request
Signals that the system interface needs to submit an external request.
Release interface
Signals that the processor is releasing the system interface to slave state.
Read Ready
Signals that an external agent can now accept a processor read.
Write Ready
Signals that an external agent can now accept a processor write request.
Valid Input
Signals that an external agent is now driving a valid address or data on the SysAD bus and a valid com-
mand or data identifier on the SysCmd bus.
Valid output
Signals that the processor is now driving a valid address or data on the SysAD bus and a valid command or
data identifier on the SysCmd bus.
System address/data bus
A 64-bit address and data bus for communication between the processor and an external agent.
System address/data check bus
An 8-bit bus containing parity check bits for the SysAD bus during data bus cycles.
System command/data identifier bus
A 9-bit bus for command and data identifier transmission between the processor and an external agent.
Reserved system command/data identifier bus parity
for the R4700 unused on input and zero on output.
Master clock
Master clock input at one half the processor operating frequency.
Master clock out
Master clock output aligned with MasterClock.
Receive clocks
Two identical receive clocks at the system interface frequency.
Transmit clocks
Two identical transmit clocks at the system interface frequency.
Reserved for future output
Always HIGH.
Reserved for future input
Should be driven HIGH.
Synchronization clock out
Must be connected to SyncIn through an interconnect that models the interconnect between MasterOut,
TClock, RClock, and the external agent.
Synchronization clock in
Synchronization clock input. See SyncOut.
Fault
Always HIGH.
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Description
December 5, 2008