MPC850DSLZQ50BU Freescale Semiconductor, MPC850DSLZQ50BU Datasheet

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... Freescale Semiconductor, Inc. Hardware Specification MPC850ABEC/D Rev. 1, 10/2002 MPC850 (Rev. A/B/C) Family Communications Controller Hardware Specifications This document contains detailed information on power considerations, AC/DC electrical characteristics, and AC timing specifications for revision A,B, and C of the MPC850 Family. This document contains the following topics: Topic Part I, “ ...

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... Freescale Semiconductor, Inc. The CPM of the MPC850 supports up to seven serial channels, as follows: • One or two serial communications controllers (SCCs). The SCCs support Ethernet, ATM (MPC850SR and MPC850DSL), HDLC and a number of other protocols, along with a transparent mode of operation. • One USB channel • ...

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... Freescale Semiconductor, Inc. Part II Features Figure 2 block diagram of the MPC850, showing its major components and the relationships among those components: Figure 2-1. MPC850 Microprocessor Block Diagram The following list summarizes the main features of the MPC850: • Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC architecture) with thirty-two 32-bit general-purpose registers (GPRs) — ...

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... Freescale Semiconductor, Inc. — 2-Kbyte instruction cache and 1-Kbyte data cache (Harvard architecture) – Caches are two-way, set-associative – Physically addressed – Cache blocks can be updated with a 4-word line burst – Least-recently used (LRU) replacement algorithm – Lockable one-line granularity — Memory management units (MMUs) with 8-entry translation lookaside buffers (TLBs) and fully-associative instruction and data TLBs — ...

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... Freescale Semiconductor, Inc. — Selectable write protection — On-chip bus arbiter supports one external bus master — Special features for burst mode support • General-purpose timers — Four 16-bit timers or two 32-bit timers — Gate mode can enable/disable counting — Interrupt can be masked on reference match and event capture • ...

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... Freescale Semiconductor, Inc. — Asynchronous HDLC to support PPP (point-to-point protocol) ® — AppleTalk — Universal asynchronous receiver transmitter (UART) — Synchronous UART — Serial infrared (IrDA) — Totally transparent (bit streams) — Totally transparent (frame based with optional cyclic redundancy check (CRC)) • ...

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... Freescale Semiconductor, Inc. — Full high: all units fully powered at high clock frequency — Full low: all units fully powered at low clock frequency — Doze: core functional units disabled except time base, decrementer, PLL, memory controller, real-time clock, and CPM in low-power standby — ...

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... Freescale Semiconductor, Inc. Table 3-2. Maximum Ratings (GND = 0V) Rating Supply voltage 1 Input voltage 2 Junction temperature Storage temperature range 1 Functional operating conditions are provided with the DC electrical specifications in Table 4-5. Absolute maximum ratings are stress ratings only; functional operation at the maxima is not guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage to the device ...

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... Freescale Semiconductor, Inc. Part IV Thermal Characteristics Table 4-3 shows the thermal characteristics for the MPC850. Table 4-3. Thermal Characteristics Characteristic 1 Thermal resistance for BGA Thermal Resistance for BGA (junction-to-case) 1 For more information on the design of thermal vias on multilayer boards and BGA layout considerations in general, refer to AN-1231/D, offi ...

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... Freescale Semiconductor, Inc. Table 4-5. DC Electrical Specifications (continued) Characteristic Input low voltage EXTAL, EXTCLK input high voltage Input leakage current, Vin = 5.5 V (Except TMS, TRST, DSCK and DSDI pins) Input leakage current, Vin = 3.6V (Except TMS, TRST, DSCK and DSDI pins) ...

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... Freescale Semiconductor, Inc INT I watts—chip internal power , INT Power dissipation on input and output pins—user determined I/O For most applications P < 0.3 I/O approximate relationship between ÷ 273° Solving equations (1) and (2) for K gives: + 273°C) + θ • where constant pertaining to the particular part. K can be determined from equation ...

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... Freescale Semiconductor, Inc. Layout Practices Part VI Bus Signal Timing Table 6-6 provides the bus operation timing for the MPC850 at 50 MHz, 66 MHz, and 80 MHz. Timing information for other bus speeds can be interpolated by equation using the MPC850 Electrical Specifications Spreadsheet found at http://www.mot.com/netcomm. ...

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... Freescale Semiconductor, Inc. Table 6-6. Bus Operation Timing Num Characteristic B7b CLKOUT to BR, BG, FRZ, VFLS[0–1], VF[0–2] IWP[0–2], 4 LWP[0–1], STS invalid B8 CLKOUT to A[6–31], RD/WR, BURST, D[0–31], DP[0–3] valid B8a CLKOUT to TSIZ[0–1], REG, RSV, AT[0–3] BDIP, PTR valid B8b CLKOUT to BR, BG, VFLS[0– ...

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... Freescale Semiconductor, Inc. Layout Practices Table 6-6. Bus Operation Timing Num Characteristic B19 CLKOUT rising edge to D[0–31], 7 DP[0–3] valid (hold time) B20 D[0–31], DP[0–3] valid to CLKOUT falling edge (setup 8 time) B21 CLKOUT falling edge to D[0–31], DP[0–3] valid (hold ...

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... Freescale Semiconductor, Inc. Table 6-6. Bus Operation Timing Num Characteristic B28b CLKOUT falling edge to CS negated GPCM write access TRLX = 0,1 CSNT = 1, ACS = 10 or ACS = 11, EBDF = 0 B28c CLKOUT falling edge to WE[0–3] negated GPCM write access TRLX = 0,1 CSNT = 1 write access TRLX = 0, CSNT = ...

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... Freescale Semiconductor, Inc. Layout Practices Table 6-6. Bus Operation Timing Num Characteristic B29h WE[0–3] negated to D[0–31], DP[0–3] high-Z GPCM write access TRLX = 0, CSNT = 1, EBDF = 1 B29i CS negated to D[0–31], DP[0–3] high-Z GPCM write access, TRLX = 1, CSNT = 1, ACS = 10 or ACS = 11, EBDF = 1 B30 CS, WE[0– ...

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... Freescale Semiconductor, Inc. Table 6-6. Bus Operation Timing Num Characteristic B31a CLKOUT falling edge to CS valid - as requested by control bit CST1 in the corresponding word in the UPM B31b CLKOUT rising edge to CS valid - as requested by control bit CST2 in the corresponding word in the UPM B31c CLKOUT rising edge to CS valid ...

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... Freescale Semiconductor, Inc. Layout Practices Table 6-6. Bus Operation Timing Num Characteristic B34 A[6–31] and D[0–31 valid - as requested by control bit CST4 in the corresponding word in the UPM B34a A[6–31] and D[0–31 valid - as requested by control bit CST1 in the corresponding word in the UPM B34b A[6– ...

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... Freescale Semiconductor, Inc. 1 The minima provided assume load, whereas maxima assume a 50pF load. For frequencies not marked on the part, new bus timing must be calculated for all frequency-dependent AC parameters. Frequency-dependent AC parameters are those with an entry in the FFactor column. AC parameters without an FFactor entry do not need to be calculated and can be taken directly from the frequency column corresponding to the frequency marked on the part ...

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... Freescale Semiconductor, Inc. Layout Practices CLKOUT Outputs Outputs Inputs Inputs A Maximum output delay specification B Minimum output hold time C Minimum input setup time specification D Minimum input hold time specification 20 MPC850 (Rev. A/B/C) Hardware Specifications For More Information On This Product Figure 6-2. Control Timing Go to: www ...

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... Freescale Semiconductor, Inc. Figure 6-3 provides the timing for the external clock. Figure 6-3. External Clock Timing Figure 6-4 provides the timing for the synchronous output signals. CLKOUT Output Signals Output Signals Output Signals Figure 6-4. Synchronous Output Signals Timing MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifi ...

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... Freescale Semiconductor, Inc. Layout Practices Figure 6-5 provides the timing for the synchronous active pull-up and open-drain output signals. Figure 6-5. Synchronous Active Pullup and Open-Drain Outputs Signals Timing Figure 6-6 provides the timing for the synchronous input signals. CLKOUT , , , ...

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... Freescale Semiconductor, Inc. Figure 6-7 provides normal case timing for input data. Figure 6-7. Input Data Timing in Normal Case Figure 6-8 provides the timing for the input data controlled by the UPM in the memory controller. Figure 6-8. Input Data Timing when Controlled by UPM in the Memory Controller MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifi ...

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... Freescale Semiconductor, Inc. Layout Practices Figure 6-9 through Figure 6-12 provide the timing for the external bus read controlled by various GPCM factors. CLKOUT TS A[6:31] CSx OE WE[0:3] D[0:31], DP[0:3] Figure 6-9. External Bus Read Timing (GPCM Controlled—ACS = 00) 24 MPC850 (Rev. A/B/C) Hardware Specifications For More Information On This Product, Go to: www ...

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... Freescale Semiconductor, Inc. CLKOUT TS A[6:31] CSx OE D[0:31], DP[0:3] Figure 6-10. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10) Figure 6-11. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11) MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications For More Information On This Product, B22a Go to: www ...

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... Freescale Semiconductor, Inc. Layout Practices Figure 6-12. External Bus Read Timing (GPCM Controlled—TRLX = 1, ACS = 10, 26 MPC850 (Rev. A/B/C) Hardware Specifications For More Information On This Product, ACS = 11) Go to: www.freescale.com MOTOROLA ...

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... Freescale Semiconductor, Inc. Figure 6-13 through Figure 6-15 provide the timing for the external bus write controlled by various GPCM factors. Figure 6-13. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 0) MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications For More Information On This Product, Go to: www ...

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... Freescale Semiconductor, Inc. Layout Practices Figure 6-14. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 1) 28 MPC850 (Rev. A/B/C) Hardware Specifications For More Information On This Product, Go to: www.freescale.com MOTOROLA ...

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... Freescale Semiconductor, Inc. Figure 6-15. External Bus Write Timing (GPCM Controlled—TRLX = 1, CSNT = 1) Figure 6-16 provides the timing for the external bus controlled by the UPM. MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications For More Information On This Product, Go to: www.freescale.com Layout Practices ...

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... Freescale Semiconductor, Inc. Layout Practices Figure 6-16. External Bus Timing (UPM Controlled Signals) Figure 6-17 provides the timing for the asynchronous asserted UPWAIT signal controlled by the UPM. 30 MPC850 (Rev. A/B/C) Hardware Specifications For More Information On This Product, Go to: www.freescale.com MOTOROLA ...

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... Freescale Semiconductor, Inc. Figure 6-17. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Figure 6-18 provides the timing for the asynchronous negated UPWAIT signal controlled by the UPM. Figure 6-18. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Figure 6-19 provides the timing for the synchronous external master access controlled by the GPCM ...

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... Freescale Semiconductor, Inc. Layout Practices Figure 6-19. Synchronous External Master Access Timing (GPCM Handled ACS = 32 MPC850 (Rev. A/B/C) Hardware Specifications For More Information On This Product, 00) Go to: www.freescale.com MOTOROLA ...

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... Freescale Semiconductor, Inc. Figure 6-20 provides the timing for the asynchronous external master memory access controlled by the GPCM. Figure 6-20. Asynchronous External Master Memory Access Timing (GPCM Figure 6-21 provides the timing for the asynchronous external master control signals negation. Figure 6-21. Asynchronous External Master—Control Signals Negation Timing Table 6-7 provides interrupt timing for the MPC850 ...

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... Freescale Semiconductor, Inc. Layout Practices 1 The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as level sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference to the CLKOUT. ...

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... Freescale Semiconductor, Inc. Figure 6-22 provides the interrupt detection timing for the external level-sensitive lines. Figure 6-22. Interrupt Detection Timing for External Level Sensitive Lines Figure 6-23 provides the interrupt detection timing for the external edge-sensitive lines. Figure 6-23. Interrupt Detection Timing for External Edge Sensitive Lines Table 6-8 shows the PCMCIA timing for the MPC850 ...

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... Freescale Semiconductor, Inc. Layout Practices Table 6-8. PCMCIA Timing (continued) Num Characteristic CLKOUT to ALE negate time PCWE, IOWR negated to D[0–31] 1 invalid. WAIT_B valid to CLKOUT rising edge. CLKOUT rising edge to WAIT_B invalid. 1 PSST = 1. Otherwise add PSST times cycle time. PSHT = 0. Otherwise add PSHT times cycle time. ...

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... Freescale Semiconductor, Inc. Figure 6-25 provides the PCMCIA access cycle timing for the external bus write. Figure 6-25. PCMCIA Access Cycles Timing External Bus Write Figure 6-26 provides the PCMCIA WAIT signals detection timing. WAIT_B Figure 6-26. PCMCIA WAIT Signal Detection Timing MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifi ...

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... Freescale Semiconductor, Inc. Layout Practices Table 6-9 shows the PCMCIA port timing for the MPC850. Table 6-9. PCMCIA Port Timing Num Characteristic CLKOUT to OPx valid HRESET negated to OPx drive IP_Xx valid to CLKOUT rising edge CLKOUT rising edge to IP_Xx invalid 1 OP2 and OP3 only. ...

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... Freescale Semiconductor, Inc. Table 6-10 shows the debug port timing for the MPC850. Table 6-10. Debug Port Timing Num Characteristic DSCK cycle time DSCK clock pulse width DSCK rise and fall times DSDI input data setup time DSDI data hold time ...

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... Freescale Semiconductor, Inc. Layout Practices Table 6-11 shows the reset timing for the MPC850. Num Characteristic CLKOUT to HRESET high impedance CLKOUT to SRESET high impedance RSTCONF pulse width Configuration data to HRESET rising edge set up time Configuration data to RSTCONF rising edge set up time Confi ...

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... Freescale Semiconductor, Inc. Figure 6-32 provides the reset timing for the data bus weak drive during configuration. Figure 6-32. Reset Timing—Data Bus Weak Drive during Configuration Figure 6-33 provides the reset timing for the debug port configuration. ...

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... Freescale Semiconductor, Inc. Layout Practices Part VII IEEE 1149.1 Electrical Specifications Table 7-12 provides the JTAG timings for the MPC850 as shown in Figure 7-34 to Figure 7-37. Num Characteristic TCK cycle time TCK clock pulse width measured at 1.5 V TCK rise and fall times ...

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... Freescale Semiconductor, Inc. Figure 7-35. JTAG Test Access Port Timing Diagram Figure 7-36. JTAG TRST Timing Diagram Figure 7-37. Boundary Scan (JTAG) Timing Diagram Part VIII CPM Electrical Characteristics This section provides the AC and DC electrical specifications for the communications processor module (CPM) of the MPC850. ...

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... Freescale Semiconductor, Inc. PIO AC Electrical Specifications 8.1 PIO AC Electrical Specifications Table 8-13 provides the parallel I/O timings for the MPC850 as shown in Figure 8-38. Table 8-13. Parallel I/O Timing Num 29 Data-in setup time to clock high 30 Data-in hold time from clock high ...

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... Freescale Semiconductor, Inc. Figure 8-39. IDMA External Requests Timing Diagram Figure 8-40. SDACK Timing Diagram—Peripheral Write, TA Sampled Low at the MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications For More Information On This Product, IDMA Controller AC Electrical Specifications Falling Edge of the Clock Go to: www.freescale.com ...

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... Freescale Semiconductor, Inc. IDMA Controller AC Electrical Specifications Figure 8-41. SDACK Timing Diagram—Peripheral Write, TA Sampled High at the 46 MPC850 (Rev. A/B/C) Hardware Specifications For More Information On This Product, Falling Edge of the Clock Go to: www.freescale.com MOTOROLA ...

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... Freescale Semiconductor, Inc. Figure 8-42. SDACK Timing Diagram—Peripheral Read 8.3 Baud Rate Generator AC Electrical Specifications Table 8-15 provides the baud rate generator timings as shown in Figure 8-43. Table 8-15. Baud Rate Generator Timing Num 50 BRGO rise and fall time 51 BRGO duty cycle ...

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... Freescale Semiconductor, Inc. Timer AC Electrical Specifications 8.4 Timer AC Electrical Specifications Table 8-16 provides the baud rate generator timings as shown in Figure 8-44. Num 61 TIN/TGATE rise and fall time 62 TIN/TGATE low time 63 TIN/TGATE high time 64 TIN/TGATE cycle time 65 CLKO high to TOUT valid Figure 8-44 ...

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... Freescale Semiconductor, Inc. Table 8-17. SI Timing (continued) Num Characteristic 74 L1xCLK edge to L1RSYNC, L1TSYNC, invalid (SYNC hold time) 75 L1RSYNC, L1TSYNC rise/fall time 76 L1RXD valid to L1xCLK edge (L1RXD setup time) 77 L1xCLK edge to L1RXD invalid (L1RXD hold time) 78 L1xCLK edge to L1STn valid 78A L1SYNC valid to L1STn valid ...

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... Freescale Semiconductor, Inc. Serial Interface AC Electrical Specifications L1RCLK (FE=0, CE=0) (Input) 71 L1RCLK (FE=1, CE=1) (Input) L1RSYNC (Input) 73 L1RxD (Input) 76 L1STn (Output) Figure 8-45. SI Receive Timing Diagram with Normal Clocking (DSC = 0) 50 MPC850 (Rev. A/B/C) Hardware Specifications For More Information On This Product, ...

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... Freescale Semiconductor, Inc. L1RCLK (FE=1, CE=1) (Input) 82 L1RCLK (FE=0, CE=0) (Input) 75 L1RSYNC (Input L1RXD (Input) 76 L1ST(4-1) (Output) L1CLKO (Output) Figure 8-46. SI Receive Timing with Double-Speed Clocking (DSC = 1) MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications For More Information On This Product, Serial Interface AC Electrical Specifications ...

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... Freescale Semiconductor, Inc. Serial Interface AC Electrical Specifications L1TCLK (FE=0, CE=0) (Input) 71 L1TCLK (FE=1, CE=1) (Input) 73 L1TSYNC (Input) 80a L1TxD BIT0 (Output L1STn (Output) Figure 8-47. SI Transmit Timing Diagram 52 MPC850 (Rev. A/B/C) Hardware Specifications For More Information On This Product TFSD to: www.freescale.com ...

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... Freescale Semiconductor, Inc. L1RCLK (FE=0, CE=0) (Input) 82 L1RCLK (FE=1, CE=1) (Input) TFSD=0 75 L1RSYNC (Input L1TXD BIT0 (Output) 80 78a L1ST(4-1) (Output L1CLKO (Output) Figure 8-48. SI Transmit Timing with Double Speed Clocking (DSC = 1) MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications For More Information On This Product, ...

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L1RCLK (Input L1RSYNC (Input L1TXD B17 B16 B15 B14 B13 (Output L1RXD B17 B16 B15 B14 B13 (Input) 76 L1ST(4-1) (Output) 85 L1RQ (Output) 86 L1GR (Input) 6 ...

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... Freescale Semiconductor, Inc. 8.6 SCC in NMSI Mode Electrical Specifications Table 8-18 provides the NMSI external clock timing. Table 8-18. NMSI External Clock Timing Num Characteristic 100 RCLKx and TCLKx frequency table) 101 RCLKx and TCLKx width low 102 RCLKx and TCLKx rise/fall time ...

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... Freescale Semiconductor, Inc. SCC in NMSI Mode Electrical Specifications Figure 8-50 through Figure 8-52 show the NMSI timings. Figure 8-50. SCC NMSI Receive Timing Diagram Figure 8-51. SCC NMSI Transmit Timing Diagram 56 MPC850 (Rev. A/B/C) Hardware Specifications For More Information On This Product, Go to: www ...

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... Freescale Semiconductor, Inc. Figure 8-52. HDLC Bus Timing Diagram 8.7 Ethernet Electrical Specifications Table 8-20 provides the Ethernet timings as shown in Figure 8-53 to Figure 8-55. Num 120 CLSN width high 121 RCLKx rise/fall time ( for all specs in this table) 122 RCLKx width low ...

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... Freescale Semiconductor, Inc. Ethernet Electrical Specifications Table 8-20. Ethernet Timing (continued) Num 133 TENA active delay (from TCLKx rising edge) 134 TENA inactive delay (from TCLKx rising edge) 138 CLKOUT low to SDACK asserted 139 CLKOUT low to SDACK negated 1 The ratios SyncCLK/RCLKx and SyncCLK/TCLKx must be greater or equal to 2/1. ...

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... Freescale Semiconductor, Inc. Figure 8-55. Ethernet Transmit Timing Diagram 8.8 SMC Transparent AC Electrical Specifications Figure 8-21 provides the SMC transparent timings as shown in Figure 8-56. Table 8-21. Serial Management Controller Timing Num 150 SMCLKx clock period 151 SMCLKx width low 151a ...

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... Freescale Semiconductor, Inc. SPI Master AC Electrical Specifications Figure 8-56. SMC Transparent Timing Diagram 8.9 SPI Master AC Electrical Specifications Table 8-22 provides the SPI master timings as shown in Figure 8-57 and Figure 8-58. Table 8-22. SPI Master Timing Num 160 MASTER cycle time ...

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... Freescale Semiconductor, Inc. Figure 8-57. SPI Master ( Timing Diagram Figure 8-58. SPI Master ( Timing Diagram MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications For More Information On This Product, SPI Master AC Electrical Specifications Go to: www.freescale.com 61 ...

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... Freescale Semiconductor, Inc. SPI Slave AC Electrical Specifications 8.10 SPI Slave AC Electrical Specifications Table 8-23 provides the SPI slave timings as shown in Figure 8-59 and Figure 8-60. Table 8-23. SPI Slave Timing Num 170 Slave cycle time 171 Slave enable lead time ...

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... Freescale Semiconductor, Inc. Figure 8-59. SPI Slave ( Timing Diagram MOTOROLA MPC850 (Rev. A/B/C) Hardware Specifications For More Information On This Product, SPI Slave AC Electrical Specifications Go to: www.freescale.com 63 ...

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... Freescale Semiconductor, Inc. I2C AC Electrical Specifications Figure 8-60. SPI Slave ( Timing Diagram 8. Electrical Specifications 2 2 Table 8-24 provides the I C (SCL < 100 KHz) timings. Table 8-24. I Num 200 SCL clock frequency (slave) 200 SCL clock frequency (master) 202 Bus free time between transmissions ...

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... Freescale Semiconductor, Inc. Table 8-24. I Num 208 Data setup time 209 SDL/SCL rise time 210 SDL/SCL fall time 211 Stop condition setup time 1 SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) * pre_scaler * 2). The ratio SyncClk/(BRGCLK/pre_scaler) must be greater or equal to 4/1. 2 Table 8-25 provides the I C (SCL > ...

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... Freescale Semiconductor, Inc. I2C AC Electrical Specifications 2 Figure 8-61 shows the I C bus timing. Figure 8-61. I Part IX Mechanical Data and Ordering Information Table 9-26 provides information on the MPC850 derivative devices. Table 9-26. MPC850 Family Derivatives Device Ethernet Support MPC850 N/A MPC850DE Yes ...

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... Freescale Semiconductor, Inc. Pin Assignments and Mechanical Dimensions of the PBGA Table 9-27 identifies the packages and operating frequencies available for the MPC850. Table 9-27. MPC850 Package/Frequency/Availability Package Type 256-Lead Plastic Ball Grid Array (ZT suffix) 256-Lead Plastic Ball Grid Array (CZT suffi ...

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... Freescale Semiconductor, Inc. Pin Assignments and Mechanical Dimensions of the PBGA Figure 9-62 shows the non-JEDEC pinout of the PBGA package as viewed from the top surface. PC14 PB28 PB27 PC12 TCK PC15 PA14 PA13 PA12 TMS PB26 PA15 PB30 PB29 PC13 A8 A7 PB31 ...

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... Freescale Semiconductor, Inc. Figure 9-63 shows the JEDEC pinout of the PBGA package as viewed from the top surface. PC14 PB28 PB27 PC12 TCK PC15 PA14 PA13 PA12 TMS PB26 PA15 PB30 PB29 PC13 A8 A7 PB31 TDO N/C A6 A11 A9 A12 A10 A15 A14 ...

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... Freescale Semiconductor, Inc. Pin Assignments and Mechanical Dimensions of the PBGA Figure 9-64 shows the non-JEDEC package dimensions of the PBGA. A 0.20 C 256X 0. 0. SEATING PLANE SIDE VIEW e 15X (E1 Figure 9-64. Package Dimensions for the Plastic Ball Grid Array (PBGA)—non-JEDEC Standard 70 MPC850 (Rev. A/B/C) Hardware Specifications ...

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... Freescale Semiconductor, Inc. Pin Assignments and Mechanical Dimensions of the PBGA Figure 9-65 shows the JEDEC package dimensions of the PBGA. A 0.20 C 256X 0. 0. SEATING PLANE SIDE VIEW e 15X (E1 Figure 9-65. Package Dimensions for the Plastic Ball Grid Array (PBGA)—JEDEC 71 MPC850 (Rev. A/B/C) Hardware Specifications ...

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... Freescale Semiconductor, Inc. Pin Assignments and Mechanical Dimensions of the PBGA Part X Document Revision History Table 10-28 lists significant changes between revisions of this document. Table 10-28. Document Revision History Revision Date 0.1 11/2001 Removed reference to 5 Volt tolerance capability on peripheral interface pins. ...

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... Freescale Semiconductor, Inc. Pin Assignments and Mechanical Dimensions of the PBGA THIS PAGE INTENTIONALLY LEFT BLANK 73 MPC850 (Rev. A/B/C) Hardware Specifications For More Information On This Product, Go to: www.freescale.com MOTOROLA ...

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... Freescale Semiconductor, Inc. Pin Assignments and Mechanical Dimensions of the PBGA THIS PAGE INTENTIONALLY LEFT BLANK 74 MPC850 (Rev. A/B/C) Hardware Specifications For More Information On This Product, Go to: www.freescale.com MOTOROLA ...

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... Freescale Semiconductor, Inc. Pin Assignments and Mechanical Dimensions of the PBGA THIS PAGE INTENTIONALLY LEFT BLANK 75 MPC850 (Rev. A/B/C) Hardware Specifications For More Information On This Product, Go to: www.freescale.com MOTOROLA ...

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... TECHNICAL INFORMATION CENTER: 800-521-6274 HOME PAGE: www.motorola.com/semiconductors Freescale Semiconductor, Inc. Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. ...