MC68340AG16E Freescale Semiconductor, MC68340AG16E Datasheet - Page 162
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MC68340AG16E
Manufacturer Part Number
MC68340AG16E
Description
IC MPU 32BIT 16MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68340FE25E.pdf
(441 pages)
Specifications of MC68340AG16E
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
144-LQFP
Controller Family/series
68K
Core Size
32 Bit
No. Of I/o's
16
Cpu Speed
16MHz
No. Of Timers
2
Embedded Interface Type
UART
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Processor Series
M683xx
Core
CPU32
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Details
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5.3.3.6 BIT MANIPULATION INSTRUCTIONS. Bit manipulation operations are
accomplished using the following instructions: bit test (BTST), bit test and set (BSET), bit
test and clear (BCLR), and bit test and change (BCHG). All bit manipulation operations
can be performed on either registers or memory. The bit number is specified as immediate
data or in a data register. Register operands are 32 bits long, and memory operands are 8
bits long. Table 5-8 is a summary of bit manipulation instructions.
MOTOROLA
Instruction
Instruction
SWAP
ROXL
ROXR
BCHG
BCLR
BSET
BTST
ASR
ROL
ROR
ASL
LSR
LSL
# data
# data
# data
# data
# data Dn
# data Dn
# data Dn
# data Dn
# data Dn
# data Dn
# data Dn
# data Dn
Operand
Operand
Dn, ea
Dn, ea
Dn, ea
Dn, ea
Syntax
Syntax
Dn, Dn
Dn, Dn
Dn, Dn
Dn, Dn
Dn, Dn
Dn, Dn
Dn, Dn
Dn, Dn
Freescale Semiconductor, Inc.
Dn
ea
ea
ea
ea
ea
ea
ea
ea
Table 5-8. Bit Manipulation Operations
Table 5-7. Shift and Rotate Operations
For More Information On This Product,
ea
ea
ea
ea
Operand Size
Operand Size
MC68340 USER’S MANUAL
Go to: www.freescale.com
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 32
8, 32
8, 32
8, 32
8, 32
8, 32
8, 32
8, 32
16
16
16
16
16
16
16
16
16
~( bit number of destination)
~( bit number of destination)
~( bit number of destination)
~ bit number of destination)
destination
destination
destination
C
0
X/C
X
X/C
C
MSW
Operation
Operation
LSW
Z
Z; 0
Z; 1
Z
bit of
X/C
C
X/C
bit of
bit of
X
0
0
C
5- 25
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