MC68340AG16E Freescale Semiconductor, MC68340AG16E Datasheet - Page 68
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MC68340AG16E
Manufacturer Part Number
MC68340AG16E
Description
IC MPU 32BIT 16MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68340FE25E.pdf
(441 pages)
Specifications of MC68340AG16E
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
144-LQFP
Controller Family/series
68K
Core Size
32 Bit
No. Of I/o's
16
Cpu Speed
16MHz
No. Of Timers
2
Embedded Interface Type
UART
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Processor Series
M683xx
Core
CPU32
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Details
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State 4—The MC68340 issues no new control signals during S4.
State 5—The MC68340 negates AS and DS during S5. It holds the address and data valid
during S5 to provide address hold time for memory systems. R/ W , SIZ1/SIZ0, and FC3–
FC0 also remain valid throughout S5. The external device must keep DSACK asserted
until it detects the negation of AS or DS (whichever it detects first). The device must
negate DSACK within approximately one clock period after sensing the negation of AS
or DS . DSACK
detected for the next bus cycle.
3.3.3 Read-Modify-Write Cycle
The read-modify-write cycle performs a read, conditionally modifies the data in the
arithmetic logic unit, and may write the data out to memory. In the MC68340, this
operation is indivisible, providing semaphore capabilities for multiprocessor systems.
During the entire read-modify-write sequence, the MC68340 asserts RMC to indicate that
an indivisible operation is occurring. The MC68340 does not issue a BG signal in response
to a BR signal during this operation. Figure 3-9 is an example of a functional timing
diagram of a read-modify-write instruction specified in terms of clock periods.
MOTOROLA
SIZ1–SIZ0
FC3–FC0
CLK
A31–A30
DSACKx
D15–D0
RMC
R/W
OUT
signals that remain asserted beyond this limit may be prematurely
DS
AS
Figure 3-9. Read-Modify-Write Cycle Timing
Freescale Semiconductor, Inc.
S0
For More Information On This Product,
S2
READ
MC68340 USER’S MANUAL
Go to: www.freescale.com
S4
INDIVISIBLE
CYCLE
S0
S2
WRITE
S4
S0
3- 19
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