MC68340AG16E Freescale Semiconductor, MC68340AG16E Datasheet - Page 270

• Manufacturer Part Number: MC68340AG16E
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16E

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor, Inc.
Each operand transfer in dual-address mode requires from two to five bus cycles in
response to each operand transfer request. If the source and destination operands are the
same size, two cycles will transfer the complete operand. If the source and destination
operands are different sizes, the number of cycles will vary. If the source is a long-word
and the destination is a byte, there would be one bus cycle for the read and four bus
cycles for the write. Once the DMA channel has started a dual-address operand transfer, it
must complete that transfer before releasing ownership of the bus or servicing a request
for another channel of equal or higher priority, unless one of the bus cycles is terminated
with a bus error during the transfer.
6.6.3 Channel Termination
The channel can terminate by normal completion or from an error. The status of a DMA
operation can be determined by reading the CSR. The DMA channel can also interrupt the
processor to inform it of errors, normal transfer completion, or breakpoints. The fast
termination option can also be used to provide a two-clock access for external requests.
6.6.3.1 CHANNEL TERMINATION. The channel operation can be terminated for several
reasons: the BTC is decremented to zero, a peripheral device asserts DONE during an
operand transfer, the STR bit is cleared in the CCR, a bus cycle is terminated with a bus
error, or a reset occurs.
6.6.3.2 INTERRUPT OPERATION. Interrupts can be generated by error termination of a
bus cycle or by normal channel completion. Specifically, if the CCR interrupt error (INTE)
bit is set and a bus error on source (CCR BES) bit, bus error on destination (CCR BED)
bit, or configuration error (CCR CONF) bit is set, the CCR IRQ bit is set. In this case,
clearing the INTE, BES, BED, or CONF bits causes the IRQ bit to be cleared. If the
interrupt normal (CCR INTN) bit is set and the CCR DONE bit is set, the IRQ bit is set. In
this case, clearing the INTN or the DONE bit causes the IRQ bit to be cleared. If the
interrupt breakpoint (CCR INTB) and the CSR BRKP bits are set, the IRQ bit is set.
Clearing INTB or BRKP clears IRQ.
6.6.3.3 FAST TERMINATION OPTION. Using the system integration module (SIM40) chip
select logic, the fast termination option (Figure 6-13) can be employed to give a fast bus
access of two clock cycles rather than the standard three-cycle access time for external
requests. The fast termination option is described in Section 3 Bus Operation and
Section 4 System Integration Module.
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MC68340 USER’S MANUAL
MOTOROLA
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