MC68340AG16E Freescale Semiconductor, MC68340AG16E Datasheet - Page 229

• Manufacturer Part Number: MC68340AG16E
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16E

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor, Inc.
The execution time attributed to instructions A, B, and C after considering the overlap is
illustrated in Figure 5-32. The overlap time is attributed to the execution time of the
completing instruction. The following equation shows the method for calculating the
overlap time:
Overlap = min (Tail
, Head
)
N
N+1
INSTRUCTION A
INSTRUCTION B
INSTRUCTION C
OVERLAP
OVERLAP
PERIOD
PERIOD
(ABSORBED BY
(ABSORBED BY
INSTRUCTION A)
INSTRUCTION B)
Figure 5-32. Attributed Instruction Times
5.7.1.5 EFFECTS OF WAIT STATES. The CPU32 access time for on-chip peripherals is
two clocks. While two-clock external accesses are possible when the bus is operated in a
synchronous mode, a typical external memory speed is three or more clocks.
All instruction times listed in this section are for word access only (unless an explicit
exception is given), and are based on the assumption that both instruction fetches and
operand cycles are to a two-clock memory. Any time a long access is made, time for the
additional bus cycle(s) must be added to the overall execution time. Wait states due to
slow external memory must be added to the access time for each bus cycle.
A typical application has a mixture of bus speeds—program execution from an off-chip
ROM, accesses to on-chip peripherals, storage of variables in slow off-chip RAM, and
accesses to external peripherals with speeds ranging from moderate to very slow. To
arrive at an accurate instruction time calculation, each bus access must be individually
considered. Many instructions have a head cycle count, which can overlap the cycles of
an operand fetch to slower memory started by a previous instruction. In these cases, an
increase in access time has no effect on the total execution time of the pair of instructions.
To trace instruction execution time by monitoring the external bus, note that the order of
operand accesses for a particular instruction sequence is always the same provided bus
speed is unchanged and the interleaving of instruction prefetches with operands within
each sequence is identical.
5.7.1.6 INSTRUCTION EXECUTION TIME CALCULATION. The overall execution time
for an instruction depends on the amount of overlap with previous and subsequent
instructions. To calculate an instruction time estimate, the entire code sequence must be
5-92
MC68340 USER’S MANUAL
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com