MC68340AG25E Freescale Semiconductor, MC68340AG25E Datasheet - Page 111
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MC68340AG25E
Manufacturer Part Number
MC68340AG25E
Description
IC MPU 32BIT 25MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68340FE25E.pdf
(441 pages)
Specifications of MC68340AG25E
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
144-LQFP
Controller Family/series
68K
Core Size
32 Bit
No. Of I/o's
16
Cpu Speed
25MHz
No. Of Timers
2
Embedded Interface Type
UART
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Processor Series
M683xx
Core
CPU32
Maximum Clock Frequency
25 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68340AG25E
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MC68340AG25E
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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4.2.4.1 PROGRAMMABLE FEATURES. The chip select function supports the following
programmable features:
Four Programmable Chip Select Circuits
Variable Block Sizes
Both 8- and 16-Bit Ports Supported
Write Protect Capability
Fast Termination Option
Internal DSACK Generation for External Accesses with Programmable Wait States
Full 32-Bit Address Decode with Address Space Checking
4.2.4.2 GLOBAL CHIP SELECT OPERATION. Global chip select operation allows
address decode for a boot ROM before system initialization occurs. CS0 is the global chip
select output, and its operation differs from the other external chip select outputs following
reset. When the CPU32 begins fetching after reset, CS0 is asserted for every address
until the V-bit is set in the CS0 base address register.
4-14
All four chip select circuits are independently programmable from the same list of
selectable features. Each chip select circuit has an individual base address register and
address mask register that contain the programmed characteristics of that chip select.
The base address register selects the starting address for the address block in 256-byte
increments. The address mask register specifies the size of the address block range.
The base address register V-bit indicates that the register information for that chip
select is valid. A global chip select ( CS0 ) allows address decode for a boot ROM before
system initialization occurs.
The block size, starting from the specified base address, can vary in size from 256
bytes up to 4 Gbytes in 2 n increments. The specified base address must be on a
multiple of the the block size. The block size is specified in the address mask register.
The 8-bit ports are accessible on both odd and even addresses when connected to data
bus bits 15–8; the 16-bit ports can be accessed as odd bytes, even bytes, or even
words. The port size is specified by the PS bits in the address mask register.
The WP bit in each base address register can restrict write access to its range of
addresses.
Programming the FTE bit in the base address register for the fast termination option
causes the chip select to terminate the cycle by asserting the internal DSACK early,
providing a two-cycle external access.
DSACK can be generated internally with up to three wait states for a particular device
using the DD bits in the address mask register.
The FC bits in the base address register and FCM bits in the address mask register are
used to select address spaces for which the chip selects will be asserted.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68340 USER’S MANUAL
Go to: www.freescale.com
MOTOROLA
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