MC68340AG25E Freescale Semiconductor, MC68340AG25E Datasheet - Page 188
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MC68340AG25E
Manufacturer Part Number
MC68340AG25E
Description
IC MPU 32BIT 25MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68340FE25E.pdf
(441 pages)
Specifications of MC68340AG25E
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
144-LQFP
Controller Family/series
68K
Core Size
32 Bit
No. Of I/o's
16
Cpu Speed
25MHz
No. Of Timers
2
Embedded Interface Type
UART
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Processor Series
M683xx
Core
CPU32
Maximum Clock Frequency
25 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Details
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Manufacturer
Quantity
Price
Company:
Part Number:
MC68340AG25E
Manufacturer:
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Quantity:
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Part Number:
MC68340AG25E
Manufacturer:
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Quantity:
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tracing. Priority level is then set to the level of the interrupt, and the processor fetches a
vector number from the interrupting device (CPU space $F). The fetch bus cycle is
classified as an interrupt acknowledge, and the encoded level number of the interrupt is
placed on the address bus.
If an interrupting device requests automatic vectoring, the processor generates a vector
number (25 to 31) determined by the interrupt level number.
If the response to the interrupt acknowledge bus cycle is a bus error, the interrupt is taken
to be spurious, and the spurious interrupt vector number (24) is generated.
The exception vector number, PC, and SR are saved on the supervisor stack. The saved
value of the PC is the address of the instruction that would have executed if the interrupt
had not occurred.
Priority level 7 interrupt is a special case. Level 7 interrupts are nonmaskable interrupts
(NMI). Level 7 requests are transition sensitive to eliminate redundant servicing and
resultant stack overflow. Transition sensitive means that the level 7 input must change
state before the CPU will detect an interrupt.
An NMI is generated each time the interrupt request level changes to level 7 (regardless
of priority mask value), and each time the priority mask changes from 7 to a lower number
while the request level remains at 7.
Many M68000 peripherals provide for programmable interrupt vector numbers to be used
in the system interrupt request/acknowledge mechanism. If the vector number is not
initialized after reset and if the peripheral must acknowledge an interrupt request, the
peripheral should return the uninitialized interrupt vector number (15).
See Section 3 Bus Operation for detailed information on interrupt acknowledge cycles.
5.5.2.12 RETURN FROM EXCEPTION. When exception stacking operations for all
pending exceptions are complete, the processor begins execution of the handler for the
last exception processed. After the exception handler has executed, the processor must
restore the system context in existence prior to the exception. The RTE instruction is
designed to accomplish this task.
When RTE is executed, the processor examines the stack frame on top of the supervisor
stack to determine if it is valid and determines what type of context restoration must be
performed. See 5.5.4 CPU32 Stack Frames for a description of stack frames.
For a normal four-word frame, the processor updates the SR and PC with data pulled from
the stack, increments the SSP by 8, and resumes normal instruction execution. For a six-
word frame, the SR and PC are updated from the stack, the active SSP is incremented by
12, and normal instruction execution resumes.
For a bus fault frame, the format value on the stack is first checked for validity. In addition,
the version number on the stack must match the version number of the processor that is
MOTOROLA
MC68340 USER’S MANUAL
5- 51
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