MC68340AG25E Freescale Semiconductor, MC68340AG25E Datasheet - Page 272

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MC68340AG25E

Manufacturer Part Number
MC68340AG25E
Description
IC MPU 32BIT 25MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68340AG25E

Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
144-LQFP
Controller Family/series
68K
Core Size
32 Bit
No. Of I/o's
16
Cpu Speed
25MHz
No. Of Timers
2
Embedded Interface Type
UART
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Processor Series
M683xx
Core
CPU32
Maximum Clock Frequency
25 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68340AG25E
Manufacturer:
Freescale Semiconductor
Quantity:
135
Part Number:
MC68340AG25E
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
6.7 REGISTER DESCRIPTION
The following paragraphs contain a detailed description of each register and its specific
function. Figure 6-15 is a programmer's model (register map) of all registers in the DMA
module. Each channel has an independent set of registers. For more information about a
particular register, refer to the individual register description. The ADDRESS column
indicates the offset of the register from the base address of the DMA channel. The FC
column designation of S indicates that register access is restricted to supervisor only. A
designation of S/U indicates that access is governed by the SUPV bit in the module
configuration register (MCR).
Unimplemented memory locations return logic zero when accessed. All registers support
both byte and word transfers.
6-22
Figure 6-14. Fast Termination Option (External Burst–Source Requesting)
SIZ1–SIZ0
(OUTPUT)
NOTE
FC3–FC0
CLKOUT
DSACKx
D15–D0
A31–A0
DREQx
DONEx
DACKx
1. To cause another DMA transfer, the DREQx is asserted after DACKx is asserted and before DACKx is negated.
2. DACKx and DONEx (DMA control signals) are asserted in the source (read) DMA cycle.
R/W
DS
AS
S0
CPU CYCLE
S2
S4
Freescale Semiconductor, Inc.
For More Information On This Product,
S0
DMA READ
MC68340 USER’S MANUAL
S4
Go to: www.freescale.com
S0
DMA WRITE
S4
S0
CPU CYCLE
S2
. . . . .
S4
S0
DMA READ
S4
S0
DMA WRITE
S4
S0
MOTOROLA

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