MC68020EH16E Freescale Semiconductor, MC68020EH16E Datasheet - Page 12

• Manufacturer Part Number: MC68020EH16E
• Description: IC MPU 32BIT 33MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68020EH16E

• Processor Type: M680x0 32-Bit
• Speed: 166MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16.67MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

9/29/95
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Number
Figure
Coprocessor Address Map in MC68020/EC020 CPU Space .......................... 7-7
Coprocessor Interface Register Set Map ......................................................... 7-7
Coprocessor General Instruction Format (cpGEN) .......................................... 7-8
Coprocessor Interface Protocol for General Category Instructions.................. 7-10
Coprocessor Interface Protocol for Conditional Category Instructions ............ 7-11
Branch on Coprocessor Condition Instruction Format (cpBcc.W) ................... 7-12
Branch on Coprocessor Condition Instruction Format (cpBcc.L) ..................... 7-12
Set on Coprocessor Condition Instruction Format (cpScc) .............................. 7-13
Test Coprocessor Condition, Decrement, and Branch
Trap on Coprocessor Condition Instruction Format (cpTRAPcc) ..................... 7-15
Coprocessor State Frame Format in Memory .................................................. 7-17
Coprocessor Context Save Instruction Format (cpSAVE) ............................... 7-20
Coprocessor Context Save Instruction Protocol .............................................. 7-21
Coprocessor Context Restore Instruction Format (cpRESTORE) ................... 7-22
Coprocessor Context Restore Instruction Protocol .......................................... 7-23
Control CIR Format .......................................................................................... 7-25
Condition CIR Format ...................................................................................... 7-26
Operand Alignment for Operand CIR Accesses .............................................. 7-26
Coprocessor Response Primitive Format ........................................................ 7-28
Busy Primitive Format ...................................................................................... 7-30
Null Primitive Format........................................................................................ 7-31
Supervisor Check Primitive Format.................................................................. 7-33
Transfer Operation Word Primitive Format ...................................................... 7-33
Transfer from Instruction Stream Primitive Format .......................................... 7-34
Evaluate and Transfer Effective Address Primitive Format.............................. 7-35
Evaluate Effective Address and Transfer Data Primitive Format ..................... 7-35
Write to Previously Evaluated Effective Address Primitive Format .................. 7-37
Take Address and Transfer Data Primitive Format .......................................... 7-39
Transfer to/from Top of Stack Primitive Format ............................................... 7-40
Transfer Single Main Processor Register Primitive Format ............................. 7-40
Transfer Main Processor Control Register Primitive Format ........................... 7-41
Transfer Multiple Main Processor Registers Primitive Format ......................... 7-42
Register Select Mask Format ........................................................................... 7-42
Transfer Multiple Coprocessor Registers Primitive Format.............................. 7-43
Operand Format in Memory for Transfer to –(An) ........................................... 7-44
Transfer Status Register and ScanPC Primitive Format.................................. 7-44
Take Preinstruction Exception Primitive Format .............................................. 7-45
MC68020/EC020 Preinstruction Stack Frame ................................................. 7-46
Take Midinstruction Exception Primitive Format .............................................. 7-47
MC68020/EC020 Midinstruction Stack Frame ................................................. 7-47
Take Postinstruction Exception Primitive Format............................................. 7-48
Instruction Format (cpDBcc)........................................................................... 7-14
LIST OF ILLUSTRATIONS (Continued)
Freescale Semiconductor, Inc.
For More Information On This Product,
SECTION 1: OVERVIEW
M68020 USER’S MANUAL
Go to: www.freescale.com
Title
UM Rev.1.0
MOTOROLA
Number
Page