MC68020EH16E Freescale Semiconductor, MC68020EH16E Datasheet - Page 69

• Manufacturer Part Number: MC68020EH16E
• Description: IC MPU 32BIT 33MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68020EH16E

• Processor Type: M680x0 32-Bit
• Speed: 166MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16.67MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Figure 5-18 shows a logic diagram of one method for generating byte enable signals for
16- and 32-bit ports from the SIZ1, SIZ0, A1, and A0 encodings and the R/W signal.
5.2.5 Cache Interactions
The organization and requirements of the on-chip instruction cache affect the
interpretation of DSACK1 and DSACK0. Since the MC68020/EC020 attempts to load all
instructions into the on-chip cache, the bus may operate differently when caching is
enabled. Specifically, on read cycles that terminate normally, the A1, A0, SIZ1, and SIZ0
signals do not apply.
The cache can also affect the assertion of AS and the operation of a read cycle. The
search of the cache by the processor begins when the sequencer requires an instruction.
At this time, the bus controller may also initiate an external bus cycle in case the
requested item is not resident in the instruction cache. If an internal cache hit occurs, the
external cycle aborts, and AS is not asserted.
For the MC68020, if the bus is not occupied with another read or write cycle, the bus
controller asserts the ECS signal (and the OCS signal, if appropriate). It is possible to have
ECS asserted on multiple consecutive clock cycles. Note that there is a minimum time
specified from the negation of ECS to the next assertion of ECS (refer to Section 10
Electrical Characteristics). Instruction prefetches can occur every other clock so that if,
after an aborted cycle due to an instruction cache hit, the bus controller asserts ECS on
the next clock, this second cycle is for a data fetch. Note that, if the bus controller is
executing other cycles, these aborted cycles due to cache hits may not be seen externally.
5-22
Byte
Word
3 Bytes
Long Word
Transfer Size
Table 5-7. Data Bus Byte Enable Signals for Byte, Word, and Long-Word Ports
SIZ1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
SIZ0
Freescale Semiconductor, Inc.
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
For More Information On This Product,
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
M68020 USER’S MANUAL
Go to: www.freescale.com
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D31–D24
B W L
B W L
B W L
B W L
B W
B W
B W
B W
B
B
B
B
B
B
B
B
Byte (B), Word (W) , Long-Word (L) Ports
Data Bus Active Sections
D23–D16
W L
W L
W L
W L
W L
W L
W L
—
—
W
W
W
W
W
W
W
D15–D8
—
—
—
—
—
—
—
L
L
L
L
L
L
L
L
L
MOTOROLA
D7–D0
—
—
—
—
—
—
L
L
L
L
L
L
L
L
L
L