MC68EN360ZQ25VL Freescale Semiconductor, MC68EN360ZQ25VL Datasheet - Page 241

• Manufacturer Part Number: MC68EN360ZQ25VL
• Description: IC MPU QUICC 32BIT 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EN360ZQ25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3V
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

5.7.2.12 CONTROL INSTRUCTIONS. The control instruction table indicates the number of
clock periods needed for the processor to perform the specified operation on the given
addressing mode. Footnotes indicate when to account for the appropriate EA times. The
total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/
p/w) are included in the total clock cycle number. All timing data assumes two-clock reads
and writes.
ANDI
EORI
ORI
ANDI
EORI
ORI
BSR.B
BSR.W
BSR.L
CHK
CHK
CHK2 (Save) FEA , Dn (no ex)
CHK2 (Op) FEA , Dn (no ex)
CHK2 (Save) FEA , Dn (ex)
CHK2 (Op) FEA , Dn (ex)
JMP
JSR
LEA
LINK.W An, #
LINK.L An, #
NOP
PEA
RTD
RTR
RTS
UNLK
X
NOTE: The CHK2 instruction involves a save step that other instructions do not have. To cal-
culate the total instruction time, calculate the save, the EA, and the operation execution times;
then combine in the order listed using the equations given in 5.7.1 Resource Scheduling.
=
#, SR
#, SR
#, SR
#, CCR
#, CCR
#, CCR
#
An
FEA , Dn (no ex)
FEA , Dn (ex)
CEA
CEA
CEA , An
CEA
There is one bus cycle for byte and word operands and two bus cycles for long-word
operands. For long-word bus cycles, add two clocks to the tail and to the number of
cycles.
Timing is calculated with the CPU32+ in 16-bit mode.
Instruction
Freescale Semiconductor, Inc.
For More Information On This Product,
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Go to: www.freescale.com
Head
0
0
0
2
2
2
3
3
1
2
2
1
2
1
2
0
3
0
2
0
0
0
1
1
1
1
Tail
0
0
0
0
1
0
1
0
0
0
0
0
0
2
2
2
2
2
2
2
2
2
2
2
2
2
52(X
18(X/0/0)
12(0/2/0)
12(0/2/0)
12(0/2/0)
13(0/2/2)
13(0/2/2)
13(0/2/2)
42(2/2/6)
13(0/2/2)
10(0/2/2)
10(0/3/2)
12(2/2/0)
14(3/2/0)
12(2/2/0)
6(0/2/0)
6(0/2/0)
6(0/2/0)
8(0/1/0)
3(0/1/0)
3(0/1/0)
6(0/2/0)
2(0/1/0)
2(0/1/0)
8(0/1/2)
9(2/1/0)
Cycles
2/1/6)
CPU32+