MC68EN360ZQ25VL Freescale Semiconductor, MC68EN360ZQ25VL Datasheet - Page 489

• Manufacturer Part Number: MC68EN360ZQ25VL
• Description: IC MPU QUICC 32BIT 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EN360ZQ25VL

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3V
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

The UART event register is a memory-mapped register that may be read at any time. A bit
is cleared by writing a one (writing a zero does not affect a bit’s value). More than one bit
may be cleared at a time. All unmasked bits must be cleared before the CP will clear the
internal interrupt request. This register is cleared at reset.
Bits 15–13, 10, 4—Reserved
GLr—Glitch on Rx
UART SCCE
LEGEND:
NOTES:
NOTES:
EVENTS
15
These bits should be written with zeros.
A clock glitch was detected by this SCC on the receive clock.
UART SCCE
TXD
RXD
RTS
CTS
CD
1. The first RX event assumes receive buffers are 6 bytes each.
2. The second IDL event occurs after an all-ones character is received.
3. The second RX event position is programmable based on the MAX_IDL value.
4. The BRKs event occurs after the first break character is received.
5. The CD event must be programmed in the port C parallel I/O, not in the SCC itself.
EVENTS
1. TX event assumes all seven characters were put into a single buffer and CR = 1 in the Tx BD.
2. The CTS event must be programmed in the port C parallel I/O, not in the SCC itself.
RECEIVED BY UART
TRANSMITTED BY UART
CHARACTERS
TIME
A receive control character defined not to be stored in the receive buffer.
14
—
CHARACTERS
13
LINE IDLE
CD
GLr
12
Figure 7-49. UART Interrupt Events Example
LINE IDLE
Freescale Semiconductor, Inc.
GLt
11
IDL
For More Information On This Product,
CTS
10
—
MC68360 USER’S MANUAL
Go to: www.freescale.com
10 CHARACTERS
AB
9
7 CHARACTERS
IDL
8
RX
GRA
7
CCR
BRKe
Serial Communication Controllers (SCCs)
TX
6
IDL
BRKs
CTS
5
LINE IDLE
RX
—
LINE IDLE
4
IDL
CCR
3
BRKs
BREAK
BSY
2
BRKe
TX
1
IDL
CD
RX
0