MC68EN360ZQ25VL Freescale Semiconductor, MC68EN360ZQ25VL Datasheet - Page 930
![IC MPU QUICC 32BIT 357-PBGA](/photos/6/76/67680/mfg_mpc860_series_sml.jpg)
MC68EN360ZQ25VL
Manufacturer Part Number
MC68EN360ZQ25VL
Description
IC MPU QUICC 32BIT 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN302AG20BT.pdf
(8 pages)
2.MC68EN360VR25L.pdf
(14 pages)
3.MC68EN360VR25L.pdf
(2 pages)
4.MC68EN360ZQ25VL.pdf
(962 pages)
Specifications of MC68EN360ZQ25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3V
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68EN360ZQ25VL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- MC68EN302AG20BT PDF datasheet
- MC68EN360VR25L PDF datasheet #2
- MC68EN360VR25L PDF datasheet #3
- MC68EN360ZQ25VL PDF datasheet #4
- Current page: 930 of 962
- Download datasheet (4Mb)
RISC Microcode from RAM
C.6 ENHANCED ETHERNET FILTERING
The enhanced Ethernet filtering microcode has been created to add a bit more flexibility to
the current Ethernet Controller. It allows the user to perfectly accept or reject frames with
destination addresses that are contained in a table of 24 entries. In addition to the filtering
capability, the microcode adds the ability to replace the externally sampled tag byte with one
that is extracted from the address table.
C.6.1 Key Features
C.6.2 Performance
The overhead incurred by the filtering algorithm will depend upon the number of entries in
the address table. Table C-5 shows possible configurations of other channels given the load
added by a number of entries in the address table.
C-8
• End Delimiter (ED) generation/checking
• Init Rx/Tx, Stop TX, Restart TX and Enter Hunt Mode Commands
• Token Rotation Timer, Idle Timer, Slot Timer and Time-out Timer
• Consumes 1280 bytes of the QUICC’s internal memory.
• Can accept or reject incoming frames if the destination MAC address is contained in a
• Allows a shorter list to obtain better peripheral performance.
• Can optionally tag incoming accepted frames with an 8-bit tag appended to the end of
• The filtering can be turned off to allow tagging with no frame rejection.
• Can filter on group and individual addresses.
• Is a “small” microcode (consumes 768 bytes of DPRAM).
• Filtering is only supported on one Ethernet channel (SCC1), the other channel operates
list of 24 preprogrammed entries.
the frame (rather than using a CAM).
normally.
Number of addresses
17-24
9-16
1-8
Freescale Semiconductor, Inc.
For More Information On This Product,
Table C-5. Channel Configuration
MC68360 USER’S MANUAL
Go to: www.freescale.com
Possible Configuration of Other Channels
1 x 10 Mbit Ethernet, 1 x 200 Kbit HDLC
1 x 10 Mbit Ethernet, 1 x 200 Kbit HDLC
1 x 10 Mbit Ethernet
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