MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 121

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

6.1.1 Floating-Point Data Registers (FP7–FP0)
The floating-point data registers are analogous to the integer data registers of the M68000
family. The floating-point data registers always contain extended-precision numbers. All
external operands, regardless of the data format, are converted to extended-precision val-
ues before being used in any calculation or stored in a floating-point data register. A reset
or a restore operation of the null state sets FP7–FP0 to positive, nonsignaling not-a-num-
bers (NANs).
6.1.2 Floating-Point Control Register (FPCR)
The FPCR (see Figure 6-3) contains an exception enable (ENABLE) byte that enables or
disables traps for each class of floating-point exceptions and a mode control (MODE) byte
that sets the user-selectable modes. The user can read or write to the FPCR. Motorola
reserves bits 31–16 for future definition; these bits are always read as zero and are ignored
during write operations. The reset function or a restore operation of the null state clears the
FPCR. When cleared, this register provides the IEEE 754 standard defaults.
6.1.2.1 EXCEPTION ENABLE BYTE. Each bit of the ENABLE byte (see Figure 6-3) corre-
sponds to a floating-point exception class. The user can separately enable traps for each
class of floating-point exceptions.
6.1.2.2 MODE CONTROL BYTE. The MODE byte (see Figure 6-3) controls the user-
selectable rounding modes and precisions. Zeros in this byte select the IEEE 754 standard
defaults. The rounding mode field (RND) specifies how inexact results are rounded, and the
rounding precision field (PREC) selects the boundary for rounding the mantissa.
MOTOROLA
79
64
63
Figure 6-2. Floating-Point User Programming Model
31
31
31
CONDITION
CODE
24
M68060 USER’S MANUAL
0
23
QUOTIENT
16
16
15
15
EXCEPTION
EXCEPTION
ENABLE
STATUS
8
8
7
7
EXCEPTION
ACCRUED
CONTROL
MODE
0
0
0
0
FP0
FP1
FP2
FP3
FP4
FP5
FP6
FP7
FPCR
FPSR
FPIAR
Floating-Point Unit
FLOATING-POINT
DATA REGISTERS
FLOATING-POINT
CONTROL
REGISTER
FLOATING-POINT
STATUS
REGISTER
FLOATING-POINT
INSTRUCTION
ADDRESS
REGISTER
6-3