MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 251
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MC68EC060RC66
Manufacturer Part Number
MC68EC060RC66
Description
IC MPU 32BIT 66MHZ 206-PGA
Manufacturer
Freescale Semiconductor
Specifications of MC68EC060RC66
Processor Type
M680x0 32-Bit
Speed
66MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
206-PGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Supply Voltage (max)
3.465V
Operating Supply Voltage (min)
3.135V
Operating Temp Range
0C to 110C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
206
Package Type
PGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Compliant
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8.4 RETURN FROM EXCEPTIONS
Once the processor has completed processing of all exceptions, it must restore the machine
context at the time of the initial exception before returning control to the original process.
Since the MC68060 is a complete restart machine, when the processor executes an RTE
instruction, only three fields are referenced. The stack format is accessed (SP+6) and the
frame type is first verified. If the format indicates an invalid type, a format error exception is
signaled. Otherwise, the processor accesses the SR (SP) and PC (SP+2) fields from the top
of the supervisor stack. If the PC value defines an odd address (least significant address bit
is set), then an address error exception is signaled. Note that for the format error or the
address error, the new stack frame will contain the SR value at the time the RTE’s execution
began, i.e., the SR has not been corrupted by the execution of the RTE. For either fault, the
PC is the logical address of the RTE instruction.
Given a valid stack format and a nonfaulting PC, the SR and PC are loaded with the stack
operands, the SSP adjusted by the appropriate value determined by the format field, and
control passed to the location defined by the new PC.
When the processor writes or reads a stack frame, it uses long-word operand transfers
wherever possible. Using a long-word-aligned SP enhances exception processing perfor-
mance. The processor does not necessarily read or write the stack frame data in sequential
order. The following paragraphs discuss in detail each stack frame format.
Note that unlike any of the previous M68000 processors, the MC68060 RTE instruction
treats the access error frame no differently from other frames.
8.4.1 Four-Word Stack Frame (Format $0)
If a four-word stack frame is on the stack and an RTE instruction is encountered, the pro-
cessor updates the SR and PC with the data read from the stack, increments the stack
pointer by eight, and resumes normal instruction execution
MOTOROLA
SP
+$02
+$06
15
FOUR-WORD STACK FRAME–FORMAT $0
0 0 0 0
Stack Frames
PROGRAM COUNTER
STATUS REGISTER
VECTOR OFFSET
M68060 USER’S MANUAL
0
• Interrupt
• Format Error
• TRAP #N
• Illegal Instruction
• A-Line Instruction
• F-Line Instruction
• Privilege Violation
• Floating-Point Pre-Instruction
• Unimplemented Integer
• Unimplemented Effective Ad-
dress
Exception Types
• Next Instruction
• RTE or FRESTORE Instruc-
• Next Instruction
• Illegal Instruction
• A-Line Instruction
• F-Line Instruction
• First Word of Instruction
• Floating-Point Instruction
• Unimplemented Integer In-
• Instruction That Used the Un-
tion
struction
implemented Effective Ad-
dress
Causing Privilege Violation
Stacked PC Points To
Exception Processing
8-19
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