MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 255

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

RW—Read and Write
SIZE—Transfer Size
TT—Transfer Type
TM—Transfer Modifier
PBE—Push Buffer Bus Error
SBE—Store Buffer Bus Error
PTA—Pointer A Fault
PTB—Pointer B Fault
IL—Indirect Level Fault
MOTOROLA
A read-modify-write indicates that the referenced address is capable of being read and
written. For example, for an ADD D0,<ea> instruction, the memory operand is read, mod-
ified, and then written by this instruction. A read-modify-write does not imply a “locked”
sequence.
The SIZE field corresponds to the original access size. If a data cache line read results
from a read miss and the line read encounters a bus error, the SIZE field in the resulting
stack frame indicates the size of the original read generated by the execution unit.
00 = Undefined, reserved
01 = Write
10 = Read
11 = Read-Modify-Write
00 = Byte
01 = Word
10 = Long
11 = Double Precision or MOVE16
This field defines the TT1–TT0 signal encoding for the faulted access.
This field defines the TM2–TM0 signal encoding for the faulted access.
0 = Fault not caused by a bus error (TEA asserted) during a push buffer write.
1 = Fault caused by a bus error (TEA asserted) during a push buffer write.
0 =Fault not caused by a bus error (TEA asserted) during a store buffer write.
1 =Fault caused by a bus error (TEA asserted) during a store buffer write.
0 =Fault not due to an invalid root level descriptor.
1 =Fault due to an invalid root level descriptor.
0 =Fault not due to an invalid pointer level descriptor.
1 =Fault due to an invalid pointer level descriptor.
0 =Fault not due to encountering a second indirect page descriptor.
1 =Fault due to encountering a second indirect page descriptor.
M68060 USER’S MANUAL
Exception Processing
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