MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 138

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Floating-Point Unit
A floating-point unimplemented instruction exception occurs when the processor attempts
to execute an instruction word pattern that begins with $F, the processor recognizes this bit
pattern as an MC68881 instruction, the FPU is enabled via the processor control register
(PCR), but the floating-point instruction is not implemented in the MC68060 FPU. This
exception corresponds to vector number 11 and shares this vector with the floating-point dis-
abled and the unimplemented F-line exceptions. A stack frame of type 2 is generated when
this exception is reported. The stacked PC points to the logical address of the next instruc-
tion after the floating-point instruction. In addition, the effective address of the floating-point
operand in memory (if any) is calculated and stored in the effective address field.
When an unimplemented floating-point instruction is encountered, the processor waits for
all previous floating-point instructions to complete execution. Pending exceptions are taken
and handled prior to the execution of the unimplemented instruction.
The processor begins exception processing for the unimplemented floating-point instruction
by making an internal copy of the current status register (SR). The processor then enters
the supervisor mode and clears the trace bit. The processor creates a format $2 stack frame
and saves the vector offset, PC, internal copy of the SR, and calculated effective address in
the stack frame. The saved PC value is the logical address of the instruction that follows the
unimplemented floating-point instruction. The processor generates exception vector num-
ber 11 for the unimplemented F-line instruction exception vector, fetches the address of the
F-line exception handler from the processor’s exception vector table, pushes the format $2
stack frame on the system stack, and begins execution of the exception handler after
prefetching instructions to fill the pipeline.
6-20
FMOVEM.X (dynamic register list)
F<op>.X #immediate,FPn
Table 6-11. Unimplemented Instructions
FGETMAN
FETOXM1
FGETEXP
FTRAPcc
FATANH
FSCALE
FLOG10
FCOSH
FACOS
FETOX
FATAN
FASIN
FMOD
FCOS
FScc
Unimplemented Effective Address
M68060 USER’S MANUAL
Monadic Operations
Dyadic Operations
Miscellaneous
FMOVEM.L #immediate, list
F<op>.P #immediate,FPn
of 2 or 3 control registers
FMOVECR
FTWOTOX
FLOGNP1
FTENTOX
FSINCOS
FLOGN
FTANH
FLOG2
FSINH
FDBcc
FREM
FTAN
FSIN
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MOTOROLA